Hugues Brut

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs

We developed a new Y-function-based extraction methodology to overcome the difficulties encountered by applying the conventional techniques. Our method relies on a robust recursive algorithm which requires a limited number of input parameters on which the results have a weak dependence, and so an increased reliability. The obtained results are in line with the previous methods, but show an improved accuracy. Finally, parameter extraction performed through this technique has provided accurate and reliable results over a large range of MOSFET architectures.

Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

The length of MOSFET channels is an important circuit design parameter, and this paper focuses on a new industrially-compatible technique using gate-to-channel measurements Cgc(Vg) to provide accurate extraction of the channel length. Thanks to fully-automatic probers, the technique provides large scale extractions and so, statistical-based results can be extracted with a maximized reliability. An in-depth study of parasitic capacitances has been performed to improve the extraction accuracy to within a few nanometers.

New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors

The resistance based extraction method for the determination of effective channel length and series resistance behaviour with gate bias is critically analysed. The impossibility of extracting the gate voltage variations of these parameters concurrently is demonstrated. Then a new parameter extraction procedure is given and experimentally applied to a wide range of technologies, from 1.2 /spl mu/m down to 0.1 /spl mu/m. Finally, the lack of resolution in the determination of channel length reduction and series resistance when the effective gate bias tends to zero and the impact of the substrate gate bias on these parameters is studied in detail.

New extraction method for gate bias dependent series resistance in nanometric double gate transistors

Double gate type transistors are needed for the ultimate integration on silicon, and thus extraction techniques have to be adapted. In this paper, the influence of the series resistance on the extrinsic mobility reduction parameters is analysed, in the case of a resistance varying with the gate bias. It is evidenced that both the low field and high field parameters are impacted. Then, a new approach is proposed for the extraction of the series resistance variation with the gate voltage, and applied to the analysis of gate-all-around transistors series resistance, with doped and undoped body.

A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs

In this study, a new technique to extract the S/D series resistance (R<inf>sd</inf>) from the total resistance versus transconductance gain plot R<inf>tot</inf>(1/β) is proposed. The technique only requires the measurement of I<inf>d</inf>(V<inf>gs</inf>)|<inf>Vgt</inf> and β, allowing fast and statistical analysis in an industrial context. Unlike the usual R<inf>tot</inf>(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R<inf>sd</inf>(V<inf>gs</inf>) and the effective mobility reduction factor µ<inf>eff</inf>(V<inf>gt</inf>)/µ<inf>eff</inf>(0).

Impact of gate current on first order parameter extraction in sub-0.1 /spl mu/m CMOS technologies

The impact of the gate leakage current on long MOS transistor characterization is investigated in this paper. Particularly for first order parameter extraction, a new method is proposed here to rid the gate current on advanced technologies with thin gate oxides. In linear and in strong inversion regimes, we first demonstrate experimentally a 50/50 partition of the gate current between source and drain nodes. TCAD simulations performed for several oxide thicknesses and biases also confirm this partition. The intrinsic channel current of the MOS transistor can then be isolated to extract first order parameters, especially in the case of large area devices which strongly suffer from gate leakage. We show that this I/sub G/ correction permits to extract these parameters in a more consistent way. Finally, we evaluate the extraction error induced by the gate leakage current for varying oxide thicknesses and channel lengths.

Measurement of Capacitances in Multigate Transistors by Coulomb Blockade Spectroscopy

The occurence of periodic Coulomb blockade in transistors at low temperature allows to extract the capacitances between the channel and the gate, source, and drain. This extremely sensitive method is well adapted to nanoscale devices, where these capacitances are well below the fF range and in parallel with low resistances. We applied this method to 3-D stacked MOSFETs featuring a double-gate top channel and a single-gate bottom channel. The measured gate capacitances are in excellent agreement with estimations based on the geometry, and are independent on the gate voltage. The source and drain capacitances can also be measured separately for each parallel conduction channel, even when their values are markedly different. We illustrate this case with a device with one dominating double-gate channel and a buried, single-gate channel which is not detectable at 300 K and contributes for less than 5% to the total conductance at 4.2 K.