Hui Dong Lee

A 2×2 MIMO multi-band RF transceiver and power amplifier for compact LTE small cell base station

We present a fully integrated 2×2 MIMO CMOS LTE RF transceiver along with multi-band InGaP/GaAs HBT power amplifiers for LTE-A small cell (femtocell) base stations. The transceiver features highly integrated LNAs and drive amplifiers with 24 individual RF I/O pins. The multi-band PAs achieves ACLR <-45dBc at 25dBm with PAE >38% at 33dBm by employing a third-order intermodulation distortion (IMD3) canceling techniques. The presented SiP composed of proposed radio and PAs shows plenty of margins in radio conformal test of femtocell base station using a commercial modem.

A V-Band Current-Reused LNA With a Double-Transformer-Coupling Technique

This letter presents a current-reused V-band low-noise amplifier (LNA) with a double-transformer-coupling technique in 65nm CMOS technology. A couple of common-source (CS) stages are stacked to share current, and the double transformers are used as an RF signal path between the CS stages for both gain and stability considerations. The LNA has three CS-CS stages, and achieves a peak gain of 31.4 dB, a minimum noise figure (NF) of 4.7 dB, and a P1dB of -2 dBm over 62.9-67 GHz with a power consumption of 6 mW. The chip size is 0.66 × 0.90 mm2 including pads.

A Linear InGaP/GaAs HBT Power Amplifier Using Parallel-Combined Transistors With IMD3 Cancellation

In this letter, we present a linear InGaP/GaAs HBT power amplifier (PA) with parallel-combined transistors for small-cell applications. Ballast resistors with bypass resistors and capacitors are employed in parallel-combined transistors. When the resistors and capacitors are set to appropriate values, IMD3 components of the parallel-combined transistors are found to be out of phase with each other by 180° and are canceled out at the output. The experimental results show that the proposed HBT PA with parallel-combined transistors produces a saturated output power of 33.5 dBm at 0.88 GHz, with a power-added efficiency (PAE) of 46.1% at a 5-V supply voltage. To validate the effectiveness of the proposed HBT PA for linearity improvement, the implemented PA is also tested with a long-term evolution (LTE) signal (8.1-dB PAPR with 10-MHz bandwidth). The proposed PA achieves an adjacent channel leakage ratio (ACLR) below -45 dBc at an average power of 25.6 dBm with a PAE of 18.8% without applying predistortion.

Design of a 28-GHz low noise amplifier using 0.15-um InGaAs pHEMT E-mode technology

We present a 28-GHz low-noise amplifier (LNA) using 0.15-um InGaAs pHEMT enhancement-mode (E-mode) technology. The 28-GHz LNA exhibits a gain of 22.2 dB and a 3-dB bandwidth of 14.1 GHz (22.7–36.8 GHz) under 3-V supply with 38.5-mA current consumption. The simulation results of the LNA show a noise figure (NF) of 2.13 dB and a P1dB of 10.8 dBm. The chip size is 1488 um × 796 um.

A linear HBT power amplifier with an IMD3 reduction method for LTE-A small-cell base-station applications

A highly linear HBT power amplifier (PA) for LTE-A small-cell base-stations is presented. By separating a bias point of the PA sub-cells and combining these outputs with out-of phasing, the third-order intermodulation distortion (IMD) can be reduced. By the simulation results, the third-order IMDs are approximately -50 dBc and -43 dBc with and without the separate biasing at an output power of 29 dBm, respectively. The designed HBT PA has a gain of 31 dB, a P1dB of 35 dBm, and a PAE of 38.1% under 5 V supply voltage.

An mm-Wave VCO with a high-speed amplitude modulation

This paper describes the design of a mm-Wave oscillator with a high-speed amplitude modulation. The oscillator can be adjusted the output voltage level according to the highspeed data signal. Additionally, it can be conducted at a low-power for wireless communications by carrying out the oscillation and modulation at the same time. We have verified that the oscillator have tuning range of 52.3-53.5 GHz, phase noise of below -100 dBc/Hz at 1 MHz offset, and two different amplitude levels by the simulation while consuming only 9.3 mW.

A 1.8 V-to-2.5 V MIPI RFFE slave interface CMOS circuit

The MIPI RFFE slave interface circuit including Power-on-Reset (PoR), SCLK receiver and SDATA bidirectional transceiver has been implemented with a CMOS 250 nm process. Simulation results show that the designed circuit has SDATA output transition time (for rise and fall) of shorter than 3.3 ns at a full-speed rate of 26 MHz, which satisfies the timing requirement (<; 6.5 ns) by the specification of MIPI RFFE version 1.10. The target load capacitance that the designed MIPI RFFE slave interface circuit drives is 26 pF for the configuration of one master and eight slaves.

A low-power 50-GHz LC-VCO in a 65-nm CMOS technology

A low-power 50-GHz LC-VCO has been presented. Throughout EM analysis, an inductor having a quality factor of 14.3 was implemented with a microstrip line. The analyzed characteristics of a MOS varactor limit the LC tank performance due to its low quality factor. In order to overcome the LC tank performance and operate at low-power consumption, the negative transconductance stage was evaluated in various ways and found at the condition of the optimized MOSFET size and bias point. The proposed VCO was implemented in a 65-nm CMOS technology. The measurement results show a frequency range of 48.61 GHz ~ 50.84 GHz and an output power of -10 dBm. The required VCO current is about 4.7 mA from a 0.7 V supply.