Moon Seok Kim

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells

Vertical tunnel field-effect transistors (VTFETs) have been extensively explored to overcome the scaling limits and to improve on-current (ION) compared to standard lateral device structures for the future technologies. The benefits in terms of reduced footprint, high ION and feasibility of fabrication have been demonstrated in several works. Among various VTFETs, the asymmetric heterojunction vertical tunnel FETs (HVTFETs) have emerged as one of the promising alternatives to standard transistors for low-voltage applications. However, while such device-level benefits without parasitics have been widely investigated, logic-gate design with parasitics and layout implications are not clear. In this article, we investigate and compare the layouts and parasitic capacitances and resistances of HVTFETs with FinFETs. Due to the vertical device structure of HVTFETs, a smaller footprint is observed compared to FinFETs in cells with small fan-in. However, for high fan-in cells, HVTFETs exhibit area overheads due to infeasibility of contact sharing in parallel and series transistors. These area overheads also lead to approximately 48% higher parasitic capacitance and resistance compared to FinFETs when the number of parallel and series connections increases. Further, in order to analyze the impact of parasitics, we modeled the analytical parasitics in SPICE. The models for both HVTFETs and FinFETs with parasitics were used to simulate a 15-stage inverter-based ring oscillator (RO) in order to compare the delay and energy. Our simulation results clearly show that HVTFETs exhibit less delay at a VDD < 0.45 V and higher energy efficiency for VDDs in the range of 0.3V--0.7V, albeit at the cost of 8% performance degradation.

Steep Slope Devices: Enabling New Architectural Paradigms

The existence of domains where traditional CMOS processors are inefficient has been well-documented in the current literature. In particular, the inefficiency of general purpose CMOS designs operating at very low supply voltages is well-known, and steep sub-threshold slope technologies, such as Tunneling Field Effect Transistors (TFETs), have been demonstrated as a viable alternative for the low-voltage operation domain. However, restricting the design space of steep slope technology-based processors to near-threshold or sub-threshold general purpose processors does the technology a disservice. Steep slope (SS) architectures can simultaneously expand the frontiers of viable computers at both ends of the energy scale: On the one hand, SS architectures enable ultra-low power sensor nodes and wearable technology, while on the other, they are applicable to high powered servers and high performance computing engines. We demonstrate the benefits of adapting this technology in such non-conventional domains, while attempting to address the major challenges encountered. We explore the effect of noise and variations at various levels of abstraction, ranging from the device to the architecture, and examine various techniques to overcome them.

Enabling Power-Efficient Designs with III-V Tunnel FETs

III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter

This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog-to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31.4 dB for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V.

A Study of Seamless Handover Service and QoS in Heterogeneous Wireless Networks

The integration of WLAN and beyond 3G mobile networks offers the possibility of achieving anytime and anywhere Internet access. Moreover the requests for seamless multimedia services and the quality of service (QoS) support have been one of key issues in wireless networks. Therefore the researches relative to seamless multimedia service and QoS over heterogeneous wireless networks have been progressing rapidly. In this paper, we propose interworking architecture for supporting seamless multimedia service and QoS over WLAN and WiBro networks. Based on the proposed inter-working architecture, we also provide both the seamless handover architecture such an inter-network vertical handover and the QoS-aware wireless medium access control (MAC) scheme.

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at VDD.

Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs

Steep-slope heterojunction tunnel field-effect transistor (HTFET) devices promise new opportunities beyond CMOS in low-power high-performance communication applications. In this paper, the circuit design optimization of a low-power 14-bit 1-GS/s current-steering digital-to-analog converter (DAC) using 0.4/0.3 V mixed-supply HTFETs is explored. Based on the device characteristics comparison and circuit analysis, it is shown in this paper that HTFET endorses significant differences in both I -V and C -V due to the steep-slope tunneling mechanism and a nature of vertically fabricated structure. While such differences significantly affect the circuit design corners, this paper gives the device-circuit co-optimization for the HTFET DAC, reaching at higher current source output impedance, less nonlinear switching glitch distortions, and thus superior spectral performance over the Si-CMOS DAC. HTFET device variation is also discussed, and calibration techniques are adopted for the static matching accuracy.

Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs

Vertical transistors are one of the promising alternatives to standard lateral device structures in future technologies due to benefits in terms of reduced footprint and feasibility of fabrication of hetero junction structures. While such device-level benefits have been widely explored, the circuit and layout-level implications of vertical transistors require further analysis. In this work, we carry out a systematic layout and circuit analysis for 20nm vertical transistors, namely symmetrical vertical MOSFET and asymmetrical hetero junction tunnel FET (HTFET), and present a detailed comparison with 20nm Fin FETs. Our analysis clearly outlines the differences from the perspective of layouts and the performance/power of standard cells. The absence of width quantization in vertical FETs and steep switching characteristics in HTFETs result in larger drive strengths compared to Fin FETs. However, for high fan-in cells, vertical transistors show area overheads due to infeasibility of contact sharing in parallel and series transistors. For each type of device, we synthesized a 32-bit carry look ahead adder and compared energy, delay and area, taking into account layout differences due to the device structures. Our analysis shows that in spite of area overhead for some cells, high drive-strength in HTFET cells brings advantages in both area and energy over both Fin FETs and vertical MOSFETs at VDD <; 0.6V.

Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective

Spin-based memories have shown an immense promise for on-chip memory applications due to the possibilities of introducing non-volatility in caches employing a CMOS compatible process. Non-volatility leads to zero-standby leakage. However, at the same time, exploration of energy-efficient read and write mechanisms is important to lower the overall energy-consumption of an MRAM cache. Magnetization control employing spin-hall effect is one of the most promising approaches to enhance the write energy efficiency. A separate path for the read which comprises of a magnetic tunnel junction (MTJ) offers the benefits of simultaneous optimization of the read and write operations. In fact, spin-hall effect also leads to the possibility of designing cells with differential sensing. However, the advantages of a differential read over a single-ended read in terms of higher read speed and better noise immunity comes at the cost of larger number of access transistors, which may translate to lower integration density. In this paper, we perform a comparative analysis of spin-hall effect (SHE) based MRAM cells with single-ended and differential read mechanisms in terms of the cell area, read performance and read stability. We perform a detailed layout analysis based on Fin FET technology to evaluate the impact of introducing differential sensing on cell area. Our analysis shows that when the layout area is determined by the pitch of the bit-line and source-line metal tracks, the differential cell shows 1.5X increase in the cell area compared to the single-ended SHE MRAM. The area increase is 2X if the read access transistor determines the layout footprint. However, the differential sensing offers the advantages of ~48% increase in the read performance along with 6% to 9% boost in the read stability compared to the single-ended SHE MRAM. At iso-area, the differential cell shows ~24% lower read time and 12% higher read disturb margin with a similar write performance and power. Our analysis also presents other layout-driven perspectives on the design of differential and single-ended SHE MRAMs.

A study of QoS-aware MAC protocol with network adaptation

A number of QoS-aware medium access control (MAC) schemes have been introduced to extend the legacy IEEE 802.11 MAC protocol which has not guaranteed any service differentiation. However, none of those schemes fulfill both QoS features and channel efficiency although these support the service differentiation based on priority. This paper presents a novel MAC scheme for enhancements of both QoS and medium efficiency. In the proposed scheme, referred to as enhanced distributed coordination function with network adaptation (EDCF-NA), we modify the existing backoff algorithm and employ a new mechanism called inter frame space (IFS) control. These newly developed methods use smart factors denoted by ACK rate, which is involved by the entire network faults such as collisions and drops, and network load threshold (TH). In addition, our approaches are evaluated by NS-2 simulations and compared the performance of other MAC protocols