Huijung Kim

A New RF CMOS Gilbert Mixer With Improved Noise Figure and Linearity

The noise figure of an RF CMOS mixer is strongly affected by flicker noise. The noise figure can be improved using pMOS switch circuits, which insert current at the on/off crossing instants of the local oscillator switch stage because the circuits reduce the flicker noise injection. When it is applied to a conventional Gilbert mixer, the injection efficiency and linearity are degraded by the nonlinear parasitic capacitances of the pMOS switch circuits and the leakage through the parasitic path. We propose the pMOS switch circuits with an inductor, which tunes out the parasitic components at 2fo and closes out the leakage path. The mixer fabricated in 0.13-mum CMOS at 2.4-GHz center frequency has provided improved characteristics for linearity and noise figure.

A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applications

This letter presents the design and experimental results of a 1.8/2.14 GHz dual-band CMOS low-noise amplifier (LNA), which is usable for code division multiple access and wideband code division multiple access applications. To achieve the narrow-band gain and impedance matching at both bands, an extra capacitor in parallel with the Cgs of the main transistor and a harmonic tuned load are switched. Except for the output blocking capacitor and series inductor, all components are integrated on a single-chip. The LNA is designed using a 0.13mum- CMOS process and employs a supply voltage of 1.5 V and dissipates a dc power of 7.5 mW. The measured performances are gains of 14.54 dB and 16.6 dB, and noise figures of 1.75 dB and 1.97 dB at the two frequency bands, respectively. The linearity parameters of and P1dBin are -16dBm and -5.8 dBm at the 1.8 GHz, -14.8 dBm and -5.3 dBm at the 2.14 GHz, respectively.

Phase noise optimization of CMOS VCO through harmonic tuning

An optimization technique for a low phase noise CMOS LC VCO is proposed. The combination of harmonic tuning and on-chip filtering improves both 1/f/sup 3/ and 1/f/sup 2/ phase noise more than 10 dB over a comparable reference VCO. A 2.7 V, 5.4 mA, 30% tuning range, 1 GHz voltage controlled oscillator (VCO) is designed with the technique and implemented in a 0.35 /spl mu/m CMOS process. The optimized 1 GHz CMOS differential VCO achieves -89 dBc/Hz, -116 dBc/Hz and -135 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset frequencies from the carrier, respectively.

A Low Phase Noise

A low phase noise and low power LC voltage-controlled oscillator (VCO) has been designed using a 65-nm CMOS process. The phase noise is minimized by switching the differential core using a rectangular shaped voltage waveform, which is formed by a harmonic tuned LC tank assisted by a gm3 boosting circuit. The gm3 boosting circuit effectively maximizes the slope at the zero crossing point and reduces the transition time in which the switching transistor is operated at the triode region. The rectangular switching technique has improved the phase noise of the oscillator by 10 dB. The 450 mum times 540 mum chip consumes 4.34 mW. The proposed VCO has phase noises of -83.3, -110.7, and -131.8 dBc/Hz at 10 KHz, 100 KHz, and 1 MHz offset frequencies, respectively, from the 1.6-GHz carrier frequency.

LC

A 2 GHz LC VCO with a large improvement in phase noise is designed and implemented in 0.13/spl mu/m CMOS process. It has phase noise of -100.7 dBc/Hz, -130.6 dBc/Hz, and -140.8 dBc/Hz at 100 kHz, 1 MHz, and 3 MHz offset frequencies from the carrier, respectively. The phase noise reduction of about 10 dB is observed for all controllable voltage range, as compared with a comparable conventional VCO. This VCO consumes 3.29 mA from a 1.8 V supply with the silicon area of 500 /spl mu/m /spl times/ 850 /spl mu/m.

VCO in 65 nm CMOS Process Using Rectangular Switching Technique

Previously, the arginine at hen egg‐white lysozyme 61 (HEL 61) was characterized as inhibiting T‐lymphocyte stimulation due to the inefficient binding of the arginine‐containing epitope peptide to the corresponding major histocompatibility complex class II molecules in C57BL/6 mice. In this study, we produced recombinant HEL, with arginine or alanine at HEL 61, and compared its ability to induce immune responses in mice to see whether modification of an inhibitory amino acid could enhance the immunogenicity of an inefficient antigen. Immunization of the mice with modified HEL induced strong antibody and T‐cell immune responses against the native antigen. The enhanced T‐cell immune response was due to a more specific elevation of the T‐cell responses to the HEL 46–61 epitope region than to other epitope regions, although recognition of the other epitope peptides of HEL was generally increased. Mass spectrometric analyses of the epitope peptides generated by splenic antigen‐presenting cells indicated that production of the epitope peptides encompassing HEL 46–61 was efficient using the modified antigen. These results suggest that modification of the critical amino acid residue(s) involved in hampering induction of an efficient immune response is an effective method to improve the immunogenicity of an inefficient antigen.

A low phase noise 2 GHz VCO using 0.13 /spl mu/m CMOS process

This paper reports on the design procedure and mesurement results of a Ka-band MMIC VCO utilizing a 0.15 um T-gate GaAs P-HEMT technology. A balanced buffer amplifier is also developed for assurance of output power higher than 10 dBm. The VCO with center frequency of 35 GHz exhibits a tuning range of up to 3 GHz and typical output power of 10 dBm at 35 GHz without the amplifier. The best measured phase noise at 1MHz offset is - 106 dBc/Hz. The buffer amplifier exhibits a typical gain of 5.9 dB with 15dBm output power. A lange coupler is used for a good matching between the VCO and amplifier.

Modification of the Inhibitory Amino Acid for Epitope Peptide Binding onto Major Histocompatibility Complex Class II Molecules Enhances Immunogenicity of the Antigen

A single-chip, multi-mode RF front-end circuit for W-CDMA, PCS, and GPS is implemented for direct conversion receiver. Each circuit includes a LNA, mixer and I/Q distributor. The IIP2 of this module (not in GPS band) is over +45 dBm with RLOAD tuning circuits. The noise figures are less than 3.5 dB in both W-CDMA and PCS bands, and 3.8 dB in GPS band. The silicon area is 5.06 mm2 including the PADs. For a small size implementation, the circuit is integrated into a module whose size is 18 mm by 19 mm including SAW filters. The current consumptions from a 2.7 V supply in W-CDMA, PCS, and GPS modes are 37 mA, 37 mA, and 23 mA, respectively

Monolithic Ka-band VCO with wide tuning range

In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through 0.13 ㎛ RF CMOS process for WiBro system. The designed LNA achieves +7.8 ㏈m of input-referred 3 rd -order intercept point (ⅡP3) with 13.2 ㏈ of Power Gain, 1.3 ㏈ of noise figure and 5.7 mA @1.5 V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 ㏈ without degrading other features such as gain and noise figure.