Hung-Bin Chen

Performance Comparison Between Bulk and SOI Junctionless Transistors

The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 10⁵ at <i>W</i> = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage <i>V</i>_th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration <i>N</i>_sub. The modulation range of <i>V</i>_th as <i>N</i>_sub changes from 10¹⁸ to 10¹⁹ cm^-3, which is around 30%.

Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (<i>V</i>_th) roll-off characteristics at supply voltage (<i>V</i>_DD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (<i>N</i>_ch) and Fin height (<i>H</i>)/width (<i>W</i>) on device <i>V</i>_th are also compared. In addition, the <i>V</i>_th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (<i>N</i>_sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (<i>t</i>_HL) and low-to-high delay time (<i>t</i>_LH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.

Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 108 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.

Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.

High voltage characteristics of junctionless poly-silicon thin film transistors

The breakdown voltage (VBD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state VBD of 53.4 V is several times larger than VBD of 9.5 V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications.

High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer

This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 104 s at 150 °C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.

Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory With Hybrid Trap Layer

This letter demonstrates the shape effect of suspended poly-Si nanowires (NWs) on gate-all-around TFT Flash memory. The NWs are bent into a bimodal shape by process-induced strain. The proposed dual-gate (DG) and single-gate (SG) electrodes are located on the twin peaks and single valley of the bimodal shape of the NWs. The DG structure has better program/erase characteristics and reliability than the SG structure owing to the impact of the bent NWs on the dielectric strength of tunnel oxide. Moreover, incorporation of the hybrid trap layer in the DG device yields a long retention time, with only 17% charge loss over ten years.

Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel

The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high Ion/Ioff current ratio (>107) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.

Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design

A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-μm technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (VBD) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in VBD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.