Ya-Chi Cheng

Performance Comparison Between Bulk and SOI Junctionless Transistors

The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 10⁵ at <i>W</i> = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage <i>V</i>_th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration <i>N</i>_sub. The modulation range of <i>V</i>_th as <i>N</i>_sub changes from 10¹⁸ to 10¹⁹ cm^-3, which is around 30%.

Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (<i>V</i>_th) roll-off characteristics at supply voltage (<i>V</i>_DD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (<i>N</i>_ch) and Fin height (<i>H</i>)/width (<i>W</i>) on device <i>V</i>_th are also compared. In addition, the <i>V</i>_th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (<i>N</i>_sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (<i>t</i>_HL) and low-to-high delay time (<i>t</i>_LH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.

Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 108 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.

Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

High voltage characteristics of junctionless poly-silicon thin film transistors

The breakdown voltage (VBD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state VBD of 53.4 V is several times larger than VBD of 9.5 V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications.

Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel

The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high Ion/Ioff current ratio (>107) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.

Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high ION/IOFF current ratio (>107), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (Tch) of 24 nm is 50 times smaller than conventional JL-TFT with Tch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.

A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals

This work presents gate-all-around (GAA) polycrystalline silicon (poly-Si) nanowires (NWs) channel poly-Si/SiO2/Si3N4/SiO2/poly-Si (SONOS) nonvolatile memory (NVM) with a self-assembled Si nanocrystal (Si-NC) embedded charge trapping (CT) layer. Fabrication of the Si-NCs is simple and compatible with the current flash process. The 2-bit operations based on channel hot electrons injection for programming and channel hot holes injection for erasing are clearly achieved by the localized discrete trap. In the programming and erasing characteristics studies, the GAA structure can effectively reduce operation voltage and shorten pulse time. One-bit programming or erasing does not affect the other bit. In the high-temperature retention characteristics studies, the cell embedded with Si-NCs shows excellent electrons confinement vertically and laterally. With respect to endurance characteristics, the memory window does not undergo closure after 104 program/erase (P/E) cycle stress. The 2-bit operation for GAA Si-NCs NVM provides scalability, reliability and flexibility in three-dimensional (3D) high-density flash memory applications.

A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.

Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff

A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (Vbg) has been demonstrated. By applying negative bias of Vbg = −8 V in gate length of 50 nm shows excellent SS (  108), and high Vth modulation. The increased Ion simultaneously decreased Ioff via negative Vbg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with Vbg is a promising for low power circuit, power management, and System-on-Chip applications.