Hung-Chih Chang

Strong visible photoluminescence from SiO2 nanotubes at room temperature

The optical studies of SiO2 mesoporous materials with hierarchical tubules-within-tubule structure have been investigated by photoluminescence and Fourier-transform infrared transmittance (FTIR). Our results suggest that the radiative intensity can be strongly enhanced by annealing the samples in N2 environment. From the FTIR spectra, we have pointed out that the origin responsible for the strong emission is Si–OH complexes located on nanotube surface. It has been observed that after turning off the pumping laser, the photoluminescence signal of SiO2 nanotubes can persist for several seconds, which is much longer than that of most materials performed under similar conditions. We have found that the decay of the photoluminescence signal is due to the quantum tunneling process. These are triplet and singlet states of Si–OH complexes that are responsible for the observed persistent photoluminescence.

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.

Nearly defect-free Ge gate-all-around FETs on Si substrates

The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W<inf>fin</inf>) of 52nm and L<inf>g</inf> of 183nm has I<inf>on</inf>/I<inf>off</inf> =10⁵, SS= 130mV/dec, and I<inf>on</inf>=235 µA/µm at −1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D<inf>it</inf>=2×10¹² cm⁻²eV⁻¹ is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W<inf>eff</inf>) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.

High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response

The record high peak mobility of ∼1050 cm²/V-s on (001) Ge substrate is demonstrated in NFET. High-quality Ge/GeO<inf>2</inf> interface is ensured by rapid thermal oxidation (RTO) and remote ozone plasma treatment. The best achieved subthreshold swing is 150mV/dec and the on/off ratio is 2×10⁴. The low defective n⁺/p junction produced a record high on/off ratio of 2×10⁵, an ideality factor of 1.05 and strong electroluminescence. For the first time, it is reported that the uniaxial &#60;110> tensile strain (0.08%) on &#60;110> channel direction gives the best mobility enhancement (12%) among the different strain configurations, consistent with theoretical calculation.

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced I on and nearly defect-free channels

Due to the highest electron mobility (2200 cm²/Vs) on (111) Ge surface, the n-channel triangular Ge gate-all-around (GAA) FET with (111) sidewalls on Si and L_g=350 nm shows 2x enhanced I_on of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls. A novel process to etch away the defective Ge near Ge/Si interface from epitaxial Ge grown on SOI achieves a nearly defect-free channel, good gate control triangular gate, and larger effective width. Electrostatic control of SS= 94 mV/dec (at 1V) can be further improved if superior gate stack than EOT= 5.5 nm and D_it= 1×10¹² cm^-2eV^-1 is used. The I_on can be further enhanced if the line edge roughness (LER) can be reduced. The Ge GAA n-FET is reported for the first time with CMOS compatible process, which makes the circuits integration much easier.

Interfacial layer reduction and high permittivity tetragonal ZrO2 on germanium reaching ultrathin 0.39 nm equivalent oxide thickness

The nearly free interfacial layer and the tetragonal phase ZrO2 with the high permittivity of 45 ± 3 on Ge (001) substrate lead to the equivalent oxide thickness as low as 0.39 nm and the low leakage current density of 2 × 10−3 A/cm−2. The ultrathin GeON layer formed by remote plasma treatment on GeO2/Ge can inhibit the interfacial layer regrowth by retarding the interdiffusion of Ge and O atoms. The initial ∼1 nm GeO2 layer is consumed during the remote plasma treatment, confirmed by x-ray photoelectron spectroscopy and further thinned down by post-deposition annealing to trigger the GeO desorption.

Improved SPICE macromodel of phase change random access memory

This paper presents an improved SPICE macromodel of phase change random access memory (PCRAM). Based on the circuit-based model architecture in [1], the novelty of this work lies in (1) accurate modeling the current-voltage (I-V) plot including the snapback phenomenon, and (2) solution to the falling edge problem to avoid misrepresentation of the PCRAM state, and (3) calibration of the crystallization time for potential multilevel (ML) operation of the PCRAM.

Interfacial layer-free ZrO 2 on Ge with 0.39-nm EOT, κ∼43, ∼2×10 −3 A/cm 2 gate leakage, SS =85 mV/dec, I on /I off =6×10 5 , and high strain response

0.39-nm ultrathin EOT ZrO₂ having κ value as high as ~43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH₃/H₂ remote plasma treatment (RPT) after RTO-grown ultrathin (<;1nm) GeO₂/Ge and prior to PEALD ZrO₂ leads to the formation of tetragonal phase ZrO₂ and the inhibition of GeO_x IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO₂ component formed on Ge surface. GeO diffuses into ZrO₂ layer via the interface reaction (Ge+GeO₂ → 2GeO) and stabilize the tetragonal phase ZrO₂. The gate dielectric has a leakage current ~10⁴X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high I_on/I_off of ~6×10⁵ at V_d= -1V, while nMOSFET has SS of 90 mV/dec and I_on/I_off of ~1×10⁵ at V_d=1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ~0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the <;110> channel.

Radiation Impact of EUV on High-Performance Ge MOSFETs

High-energy extremely ultraviolet (EUV)-induced Ge MOSFETs degradation is investigated. The degradation of threshold voltage, subthreshold swing (SS), and channel mobility is attributed to the generation of interface traps and oxide fixed charges. Much more severe degradation of SS and VT on n-FETs compared to p-FETs suggests that more interface defects in the upper half of Ge bandgap are generated by EUV radiation than in the lower half bandgap. The increase of interface trap is responsible for the mobility degradation of n-FETs due to Coulomb scattering.

Planar and 3D Ge FETs

The strain response of high mobility Ge nFETs, low EOT (~1 nm) ZrO₂ Ge nFETs, and triangular Ge pFinFETs are reported. The strain response of (111) substrates is smaller than (001) substrates under tensile strain along <;110> channel direction. Low EOT gate-last Ge nFETs using ZrO₂ gate dielectric with nearly no interfacial layer is demonstrated with the superior electrical performance. Moreover, the triangular Ge GAA pFinFET with fin width (W_fin) of 52nm and L_g of 183nm has I_on/I_off = 10⁵, SS= 130mV/dec, and I_on=235 A/m at -1 V. T he dislocated Ge near Ge/Si interface on SOI was etched and formed nearly defect-free channels.