Chung-Hu Ge

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications

State-of-the-art process-strained Si (PSS) technology featuring single-NiSi Schottky source/drain (S/D) and ultra-thin gate oxide of 1.2 nm is demonstrated for Lgate down to 39 nm. +10% performance boost of Schottky-barrier (SB)-PSS NMOS, as compared to its non-Schottky counterpart, is demonstrated due to series resistance reduction of the silicide S/D and enhanced strain effects. Highest SB-PSS PMOS drive current of 821 muA/mum (at VD = -1.2V and Ioff = 100 nA/mum) is recorded when integrated with recessed Si1-x Gex S/D stressor

A novel CVD-SiBCN Low-K spacer technology for high-speed applications

State-of-the-art low-K spacer technology featuring novel CVD-SiBCN material is demonstrated for the first time. A significant 20% CMOS ring speed enhancement is demonstrated with SiBCN (K=5.2) spacer, compared to Si3N4 (K=7.5) spacer, due to reduced fringing capacitance and enhanced strain effects by spacer-PSS and CESL techniques. Electron mobility is improved by 6% for long channel NMOS transistor and gm,max is increased by 11% for short 35 nm physical gate length NMOS using a preferable spacer structure that is comprised of a low stress SiBCN spacer on thin SiO2 liner and a final 600degC rapid thermal post-anneal. Superior GIDL and better gate leakage is obtained because low permittivity SiBCN alleviates gate-fringing field effects (GF effects), and device reliability is not adversely impacted by this new process.

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

The correlation between channel mobility gain (Deltamu), linear drain-current gain (DeltaI_dlin), and saturation drain-current gain (DeltaIdsat) of nanoscale strained CMOSFETs are reported. From the plots of DeltaI_dlin versus DeltaI_dsat and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R_SD,PSS) to channel resistance (R_CH,PSS) of strained CMOSFETs can be extracted. By plotting Deltamu versus DeltaI_dlin, the efficiency of Deltamu translated to DeltaI_dlin is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the DeltaI_dlin-to-Deltamu sensitivity is maintained until R_SD,PSS becomes comparable to/or higher than R_CH,PSS

Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain

Channel backscattering ratios of PMOSFETs with various embedded SiGe source/drain structures are analyzed in terms of the scattering theory. We found that both the backscattering ratio and injection velocity are greatly influenced by the location and recess depth of SiGe source/drain. Although the strain-enhanced injection velocity is beneficial to the current gain, the accompanying backscattering ratio increase adversely impacts the overall performance, and therefore a trade-off exists between injection velocity and backscattering ratio during the optimization of such strain technique. The mechanism of increased backscattering ratio under uniaxial compressive strain is also investigated

Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs

Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs are reported for the first time. Channel backscattering ratio increases and decreases under uniaxial tensile and compressive strain, respectively. It is found that in sub-100-nm devices, strain-induced modulation of carrier mean-free path for backscattering and reduction in k/sub B/T layer thickness are responsible for the different behaviors of backscattering ratio. Nevertheless, the source-side injection velocity improves irrespective of the strain polarities. The impact of channel backscattering ratio on drive current is also analyzed in terms of ballistic efficiency and injection velocity.

The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs

The influence of uniaxial process-induced strain on carrier channel backscattering in nanoscale MOSFETs is reported for the first time. It is observed that the backscattering ratio can be reduced by uniaxial tensile strain while it is increased by uniaxial compressive strain mainly due to strain-induced modulation in mean-free-path for backscattering and slight decrease in kBT layer thickness. Nevertheless, both strain polarities improve source-side injection velocity because of reduced carrier effective mass. Impact to current drive under uniaxial strain is analyzed in terms of mean-free-path, kBT layer thickness, ballistic efficiency and injection velocity.

Enhanced Performance of Strained CMOSFETs Using Metallized Source/Drain Extension (M-SDE)

We have demonstrated successfully the integration scheme of metallized source/drain extension (M-SDE) with state-of-the-art strained-Si technique. Drain currents of N-FET (Lgate = 40 nm) and P-FET (Lgate = 35 nm) with M-SDE can achieve 1620 muA/mum and 755 muA/mum at |VG-Vt| = |VD| = 1V, respectively. Superior characteristics of junction leakage and source/drain series resistance are also presented. For M-SDE CMOSFETs, the capability of exploiting strain more efficiently is corroborated by the improved stress sensitivity of linear drain current to mechanical stress. M-SDE CMOSFETs exhibit higher stress sensitivity as scaling the gate length.

Characterizing the Channel Backscattering Behavior in Nanoscale Strained Complementary Metal Oxide Semiconductor Field-Effect Transistors

This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.

A novel process-induced strained silicon (PSS) CMOS technology for high-performance applications

We report an optimized process-induced strained silicon (PSS) technology for 90nm CMOS generation and beyond. Through the superposition of various PSS techniques, up to 20% performance enhancement is achieved for both N- and PMOS at channel length down to 45nm. The PSS technology exhibits excellent gate oxide breakdown characteristics, isolation characteristics and reliability. A novel spacer-PSS technology is also proposed for the first time and /spl sim/7% enhancement in ring oscillator speed is observed.