Hushan Cui

Investigation of the interface between LPCVD-SiNx gate dielectric and III-nitride for AlGaN/GaN MIS-HEMTs

The interface between silicon nitride (SiNx) gate dielectric grown by low pressure chemical vapor deposition (LPCVD) and III-nitride heterostructure is investigated by a systematical comparison of AlGaN/GaN high-electron-mobility transistors (HEMTs) and metal-insulator-semiconductor HEMTs (MIS-HEMTs). A 20-nm LPCVD-SiNx grown at 650 °C features a high breakdown E-field of 13 MV/cm and a large conduction-band offset of 2.75 eV to GaN. High ON/OFF current ratio (∼1010) as well as breakdown voltage (∼878 V) is realized by employing the LPCVD-SiNx layer as both the gate and passivation dielectrics. Most important of all, about 2.6 × 1013 cm−2 positive fixed charges are confirmed to be present at the LPCVD-SiNx/III-nitride interface, as revealed by pulsed transfer characterizations and energy-band simulations. The trap density at LPCVD-SiNx/III-nitride interface is also experimentally determined.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low VT. Compared with halo doping with the same VT,sat at VDD = 0.8 V, despite no ION enhancement, the SPW reduces DIBL by 45% and enhances IEFF by 18%. Compared with halo doping with the same IOFF = 100 nA/μm at VDD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances ION by 5%, and improves IEFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT)

Heterogeneous Memristive Devices Enabled by Magnetic Tunnel Junction Nanopillars Surrounded by Resistive Silicon Switches

Emerging non-volatile memories (NVMs) have currently attracted great interest for their potential applications in advanced low-power information storage and processing technologies. Conventional NVMs, such as magnetic random access memory (MRAM) and resistive random access memory (RRAM) suffer from limitations of low tunnel magnetoresistance (TMR), low access speed or finite endurance. NVMs with synergetic advantages are still highly desired for future computer architectures. Here, we report a heterogeneous memristive device composed of a magnetic tunnel junction (MTJ) nanopillar surrounded by resistive silicon switches, named resistively enhanced MTJ (Re-MTJ), that may be utilized for novel memristive memories, enabling new functionalities that are inaccessible for conventional NVMs. The Re-MTJ device features a high ON/OFF ratio of >1000% and multilevel resistance behaviour by combining magnetic switching together with resistive switching mechanisms. The magnetic switching originates from the MTJ, while the resistive switching is induced by a point-switching filament process that is related to the mobile oxygen ions. Microscopic evidence of silicon aggregated as nanocrystals along the 2 edges of the nanopillars verifies the synergetic mechanism of the heterogeneous memristive device. This device may provide new possibilities for advanced memristive memory and computing architectures, e.g., in-memory computing and neuromorphics.

Impact of TaN as Wet Etch Stop Layer on Device Characteristics for Dual-Metal HKMG Last Integration CMOSFETs

TaN as wet etch stop layer is implemented in dual-metal high- k/metal gate last integration CMOSFETs. Impacts of TaN on device characteristics are investigated. With thicker TaN, flat-band voltages (Vfb) of both n- and p-FETs shift to zero value position. Sensitivities of TaN thickness on Vfb are obtained with 81 and -114 mV/nm for n- and p-FETs, respectively. It could be served as an important enhancement tuning factor for threshold voltage (Vth) adjustment in CMOSFETs due to contributions of TaN on Vth values are in the same direction. With CMOS technology moving to below 22-nm node, it is crucial to control amount of wet etch of TaN layer, otherwise device characteristics would be impacted and double hump happens.

Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical vapor deposition titanium/chemical vapor deposition titanium nitride (ALD TiN/PVD Ti/CVD TiN) MG in devices of short channels is larger than in devices of long channels. This mainly results from different ALD TiN crystal orientations for devices with different gate lengths, that is, TiN(100) for devices with short gate length, whereas TiN(111) for devices with long gate length. The WF of ALD TiN(100) is larger than TiN(111). Meanwhile, because of the property of PVD sputtering, the Ti layer is thinner in devices of short channels than in devices of long channels. Our results on MOSCAP show that the flat-band voltage (Vfb) for TiN MG with a Ti layer is reduced by 0.2 V. Taking all the aforementioned into account, Vth roll-up is suppressed as the gate length shrinks, leading to the mitigation of RSCE.

Damage free removal of nano-particles with dual-fluid spray nozzle cleaning

As continue shrinking of microelectronic device features, removal of nano-particle contaminations is becoming a major challenge in semiconductor manufacturing. After effective wafer cleaning, high particles removal efficiency must be achieved without substrate loss or damage to high aspect ratio structures. In this work, a novel dual-fluid spray nozzle was tested. The cleaning performance with control to normal dispense nozzle was investigated. Also, structural damage tests were carried out on poly-gate-stack line pattern wafers, and compared to the results acquired with megasonic cleaning. The results showed potential applications of such dual-fluid spray nozzle in sub-65nm devices manufacturing.