Hwa Nien Yu

Emission probability of hot electrons from silicon into silicon dioxide

An experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the Si‐SiO2 interface. The method is based on optically induced hot‐electron injection in polysilicon‐SiO2‐silicon field‐effect‐transistor structures of reentrant geometry. The emission probability was studied as a function of substrate doping profile, substrate voltage, gate voltage, and lattice temperature. It was found that the hot electrons could be emitted by tunneling as well as by surmounting the Schottky‐lowered barrier. Over‐the‐barrier emission dominates at large substrate voltages, where the emission probability is high, and tunnel emission becomes appreciable and may even dominate at small substrate voltages where the emission probability is low. A simple model was developed based on the assumption that only those hot electrons lucky enough to escape collision with optical phonons were emitted. Using this model, we found that the expression P=A exp(−d/λ) described very well the dependence of the emission probability on doping profile, substrate voltage, and gate voltage. Here A=2.9 is a constant, λ is the optical‐phonon‐electron collision mean free path, d is the distance from the Si‐SiO2 interface where the potential energy is equal to the ’’corrected’’ barrier of (3.1 eV−βEOX1/2 −αEOX2/3ox), βEOX1/2 is the Schottky lowering of the barrier, and αEOX2/3 is a ’’barrier‐lowering’’ term introduced to account for the probability of tunneling. The temperature dependence of the collision mean free path was found to follow the theoretical relationship λ=λo tanh(ER/2kbT), with λo=108 A and ER=0.63 eV. This model is useful for evaluating potential hot‐electron‐related instability problems in IGFET and similar structures.An experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the Si‐SiO2 interface. The method is based on optically induced hot‐electron injection in polysilicon‐SiO2‐silicon field‐effect‐transistor structures of reentrant geometry. The emission probability was studied as a function of substrate doping profile, substrate voltage, gate voltage, and lattice temperature. It was found that the hot electrons could be emitted by tunneling as well as by surmounting the Schottky‐lowered barrier. Over‐the‐barrier emission dominates at large substrate voltages, where the emission probability is high, and tunnel emission becomes appreciable and may even dominate at small substrate voltages where the emission probability is low. A simple model was developed based on the assumption that only those hot electrons lucky enough to es...

Effect of electron trapping on IGFET characteristics

At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO2 layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO2/Si3N4 as gate insulator, electron trapping is completely dominated by the Si3N4 layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO2 as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.

Electron trapping at positively charged centers in SiO2

Evidence is presented which indicates that positive oxide charge centers in thin films of thermally grown silicon dioxide are electron traps with an average capture cross section of 3±2×10−13 cm2 at room temperature and at an average oxide field of about 7×105 V/cm. Positive charge centers of other origins are also expected to be electron traps with about the same capture cross section.

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Omega-mum2 that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR > 15sigma(Rp), write threshold spread sigma(Vw)/<Vw> <7.1%, breakdown-to-write voltage margin over 0.5 V, read-induced disturbance rate below 10-9, and sufficient write endurance, and is free of unwanted write-induced magnetic reversal. The statistics suggest that a 64 Mb chip at the 90-nm node is feasible.

Threshold instability in IGFET’s due to emission of leakage electrons from silicon substrate into silicon dioxide

Experimental evidence of a new type of threshold instability in IGFET’s due to the emission of leakage electrons from the silicon substrate into SiO2 is presented. Also presented is a model relating the emission current to the leakage current components of the device. This emission phenomenon could be a serious threshold instability problem at high operating temperatures where the leakage current level is high, especially in devices with a dual dielectric as the gate insulator where the electron trap concentration is very high.

A symmetrical bipolar structure

This paper presents symmetrical bipolar-transistor structures suitable for bilateral operation. Such structures were fabricated using a technique of simultaneous-growth of epitaxial and polycrystalline Si on a stack structure. Vertical symmetrical transistors have been built and showed an emitter-base diode breakdown voltage of 7V, a current gain of 17.

Sub-nanosecond self-aligned I 2 L/MTL circuits

This paper describes a self-aligned approach to the I²L/MTL technology. Experimental ring oscillator circuits designed with 2.5 µm design rules and fabricated with this technology show a measured 0.9 ns gate delay at I<inf>c</inf>= 70 µA (fan-in=1, fan-out=3).

The evolution of FET technology for VLSI applications

An overview of the development of a 1 µm MOSFET technology using electron beam lithography for VLSI applications is described. Various aspects of the technology including device design, threshold stability, reliability studies, dimensional control and performance evaluation will be reviewed briefly. Experimental results based on a device test chip and a circuit test chip will be presented as confirmation of device design and circuit performance in a VLSI chip environment.