R.D. Isaac

The future of CMOS technology

The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are outlined. Possible solutions are briefly discussed. The ways in which these challenges will affect future growth in the industry are considered.

1.25 /spl mu/m Deep-Groove-Isolated Self-Aligned Bipolar Circuits

This paper concerns the design and characteristics of the high-performance bipolar switching devices and circuits for digital applications at lithographic dimensions of about 1 /spl mu/m. The impurity profile of the transistors is optimized for speed while maintaining sufficient current gain and punchthrough voltage. The circuits were fabricated on epitaxial wafers of a 0.5 /spl mu/m flat zone in an advanced bipolar technology featuring self-aligned polysilicon base and emitter contacts, deep-groove device isolation, and electron beam lithography. The experimental results show that n-p-n transistors exhibit a current gain greater than 40 at current densities as high as 1.3 mA//spl mu/m/sup 2/. As a result of reduced line width and polysilicon contacts, the current gain of Iateral epi-base p-n-p transistors is greater than 20 at low-current levels and remains greater than 1 at a current density as high as 0.12 mA//spl mu/m emitter edge. ECL (FI = FO = 1) circuits show a gate delay as low as 114 pS at a power dissipation of 4.9 mW. High-density I/sup 2/L/MTL circuits (average FI = 2, FO = 2.5, C/sub w/ = 90 fF) show delay of 0.91 ns at 0.17 mW. These results demonstrate that the present bipolar technology provides not only high-speed circuits, but also circuits for VLSI applications with density comparable to MOSFET.

Effect of emitter contact on current gain of silicon bipolar devices

The current gain of silicon bipolar transistors with shallow (200 nm) emitters contacted either by (i) Al, (ii) Pd<inf>2</inf>Si+Al, or (iii) n⁺polysilicon+Al are compared. For the same base doping profile, β(Al) is typically about 25% larger than β(Pd<inf>2</inf>Si+Al), while β(n⁺polysilicon+Al) is typically 3 to 7 times larger than β(Pd<inf>2</inf>Si+Al). A simple two-region (n⁺Si and n⁺polysilicon) model is presented which satisfactorily explains not only our results but also the reported results in the literature on higher current gains in transistors with emitters formed by diffusion from arsenic-implanted polysilicon.

Sub-nanosecond self-aligned I 2 L/MTL circuits

This paper describes a self-aligned approach to the I²L/MTL technology. Experimental ring oscillator circuits designed with 2.5 µm design rules and fabricated with this technology show a measured 0.9 ns gate delay at I<inf>c</inf>= 70 µA (fan-in=1, fan-out=3).

1.25&#181;m deep-groove-isolated self-aligned ECL circuits

IN THIS PAPER we report the characteristics of 1.25pm ECL circuits with maximum speed of 114ps ata power dissipation of 4.9mW. Such performance is achieved through the combination of properly designed bipolar devices and an advanced bpolar technology featuring self-ali ed polysilicon-base contact and deep-groove device isolation¿. The 1.25pm minimum feature size was defined using electron-beam lithography.

A polysilicon base bipolar transistor

We have made PNP bipolar transistors consisting of n and p type polysilicon layers on a 0.01 ohm-cm p type substrate. The object of making this device was to study minority carrier transport through the n polysilicon, although we have also succeeded in making transistors with current gains greater than 5. Preliminary results indicate strong recombination in the bulk base polysilicon, with diffusion lengths less than 40nm. The base region nearest or within, the single crystal substate is much more transparent to minority carriers. In addition, the polysilicon seems to block minority carrier injection from the substrate.

Schottky barrier diodes with self-aligned floating guard rings

Schottky barrier diodes with self-aligned guard rings are described. Two device structures compatible with the self-aligned bipolar transistor process [1] are considered. For the first structure, the diffused guard ring is in physical contact with the anode of the Schottky diode as in conventional guard ring structures. For the second structure, the guard ring is separated from the anode by a sidewall oxide of thickness less than 0.3 µm, allowing independent access to the guard ring. Near-ideal I-V characteristics are obtained for both structures. It is shown that for the latter structure the guard ring can be left floating without degrading the I-V and leakage characteristics of the Schottky diode. In this mode of operation, the advantage of the guard ring is maintained while the depletion capacitance and charge storage due to injection from the p+-n junction which reduce the effectiveness of the Schottky diode as an antisaturation device are eliminated.

Bipolar device scaling limits from tunneling in base-emitter junctions

Substantial tunneling currents in emitter-base junctions at lower doping levels than previously expected (1) have been observed, and are shown to be the result of high electric fields in shallow, scaled n+-p junctions. The distinctive form of the reverse I-V curves is theoretically explained and verified by measurements on shallow n+-p diodes. The appearance of a tunneling current is ascertained by the temperature dependence, which also allows a clear distinction of other current mechanisms. It is shown how C-V data can be analyzed to obtain an experimental value for the maximum electric field in the junction, which is essential in predicting the I-V characteristics of scaled bipolar transistors.