Tak H. Ning

Emission probability of hot electrons from silicon into silicon dioxide

An experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the Si‐SiO2 interface. The method is based on optically induced hot‐electron injection in polysilicon‐SiO2‐silicon field‐effect‐transistor structures of reentrant geometry. The emission probability was studied as a function of substrate doping profile, substrate voltage, gate voltage, and lattice temperature. It was found that the hot electrons could be emitted by tunneling as well as by surmounting the Schottky‐lowered barrier. Over‐the‐barrier emission dominates at large substrate voltages, where the emission probability is high, and tunnel emission becomes appreciable and may even dominate at small substrate voltages where the emission probability is low. A simple model was developed based on the assumption that only those hot electrons lucky enough to escape collision with optical phonons were emitted. Using this model, we found that the expression P=A exp(−d/λ) described very well the dependence of the emission probability on doping profile, substrate voltage, and gate voltage. Here A=2.9 is a constant, λ is the optical‐phonon‐electron collision mean free path, d is the distance from the Si‐SiO2 interface where the potential energy is equal to the ’’corrected’’ barrier of (3.1 eV−βEOX1/2 −αEOX2/3ox), βEOX1/2 is the Schottky lowering of the barrier, and αEOX2/3 is a ’’barrier‐lowering’’ term introduced to account for the probability of tunneling. The temperature dependence of the collision mean free path was found to follow the theoretical relationship λ=λo tanh(ER/2kbT), with λo=108 A and ER=0.63 eV. This model is useful for evaluating potential hot‐electron‐related instability problems in IGFET and similar structures.An experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the Si‐SiO2 interface. The method is based on optically induced hot‐electron injection in polysilicon‐SiO2‐silicon field‐effect‐transistor structures of reentrant geometry. The emission probability was studied as a function of substrate doping profile, substrate voltage, gate voltage, and lattice temperature. It was found that the hot electrons could be emitted by tunneling as well as by surmounting the Schottky‐lowered barrier. Over‐the‐barrier emission dominates at large substrate voltages, where the emission probability is high, and tunnel emission becomes appreciable and may even dominate at small substrate voltages where the emission probability is low. A simple model was developed based on the assumption that only those hot electrons lucky enough to es...

1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage,V_{DS} = V_{GS}, is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.

Optically induced injection of hot electrons into SiO2

An experiment using the effect of optically induced hot‐electron injection in MOS transistor structures to study electron traps in SiO2 films is described. By simultaneously monitoring the gate current and the surface channel conductance shift, information on the trapping efficiency, the capture cross sections, and the trap concentrations could be obtained. Trap centers with capture cross sections differing by more than two orders of magnitude could probably be separated and their cross sections determined depending on their concentrations. Experimental results are presented for electron traps using n ‐channel silicon‐gate structures, with SiO2 layers thermally grown in dry oxygen. Two electron‐capture cross sections of 3.3 × 10−13 and 2.4 × 10−19 cm2 were measured. Although there was evidence indicating the presence of other electron traps their capture cross sections could not be unambiguously determined. The injection current can be described by Schottky‐emission processes at an effective electron temp...

High‐field capture of electrons by Coulomb‐attractive centers in silicon dioxide

Electron capture by Coulomb‐attractive oxide‐charge centers in thin SiO2 films thermally grown on silicon was studied at room temperature and at 77°K for average oxide fields ranging from 5×105 to 3×106 V/cm. The observed capture cross section varied with the average oxide field, EOX, approximately as EOX −3. Such a strong field dependence cannot be accounted for by the Frenkel‐Poole lowering of the potential % barrier alone which predicts an EOX −3/2 dependence. It is suggested that electron heating by the oxide field is likely at these high fields. Electron heating decreases the probability of capture. The observed field dependence can be explained by a combination of Frenkel‐Poole and electron‐heating effects. Although the zero‐field capture cross section is expected to increase rapidly with decreasing lattice temperature, the observed high‐field capture cross sections were about the same at room temperature and at 77°K. Such weak dependence of the high‐field capture cross section on lattice temperatur...

Method for determining the emitter and base series resistances of bipolar transistors

A simple method for determining both the emitter and the base series resistances of bipolar transistors from the measured I - V characteristics is described. The method is based on the observation that deviation of the base current from the ideal\exp (qV_{BE}/kT)behavior at high currents can be attributed solely and relatively simply to series resistances. Series resistances determined by this method are given for sample high-speed digital bipolar transistors.

Capture cross section and trap concentration of holes in silicon dioxide

Hole trapping in thermally grown silicon‐dioxide films has been studied using optically induced hot‐hole injection in p‐channel polysilicon‐SiO2‐silicon field‐effect‐transistor structures. Analysis of the data assuming a uniform trap distribution and no detrapping gives 3.1×10−13 cm2 and 1.4×1018 cm−3 for the capture cross section and the trap concentration, respectively. Initial hole‐trapping efficiency is almost 99% for a 1000‐A SiO2 film.

Electron trapping in SiO2 due to electron‐beam deposition of aluminum

Electron trapping in the SiO2 layer of n‐channel polycrystalline silicon‐SiO2‐silicon field‐effect transistors with electron‐beam‐evaporated aluminum was studied. The increased electron trapping was attributed to the x rays generated when the electron beam impinged on the aluminum target. Traps with low‐field capture cross sections greater than 10−13 cm2 are associated with the x‐ray‐induced positively charged centers, while traps with low‐field capture cross sections of about 1×10−15 cm2 are associated with the x‐ray‐induced neutral centers. For the silicon‐gate devices, both traps could be effectively reduced by annealing in dry forming gas at 550 °C for 20 min. As reported earlier, the capture cross section of the positively charged traps has a strong field dependence of approximately E−3ox and is approximately independent of temperature. The field dependence of the capture cross section of the neutral traps is much weaker, with roughly a σ  =σ0 exp(−bEox) dependence, where σ0=1.6×10−15 cm2 and b=7.35×...

Thermal reemission of trapped electrons in SiO2

Electron trapping by neutral trap centers in SiO2 was studied at 77 K and at room temperature, using n‐channel silicon‐gate IGFET structures. The electrons were injected in the dark using the forward‐bias pulsed injection method. The results show that electron trapping by the neutral centers was one to two orders of magnitude more efficient at 77 K than at room temperature; which may be compared with the previously reported electron trapping by Coulomb‐attractive centers where the capture cross sections at room temperature and at 77 K were about the same. For injected electron concentrations of less than 1016 cm−2, more than 90% of the electron trapping at 77 K was due to shallow‐level centers where the captured electrons were thermally reemitted as the samples were warmed to room temperature. The concentrations of these shallow‐level traps in dry, wet, and HCl oxides were about the same, regardless of whether the aluminum evaporation was by electron‐beam or by rf heating in a tantalum boat. The capture c...

Effect of electron trapping on IGFET characteristics

At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO2 layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO2/Si3N4 as gate insulator, electron trapping is completely dominated by the Si3N4 layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO2 as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >