Hwa-Sun Park

Effect of a high-temperature pre-bake treatment on whisker formation under various thermal and humidity conditions for electrodeposited tin films on copper substrates

The effect of high-temperature pre-bake treatment on whisker formation was studied under various thermal and/or humidity and plating conditions for thin tin films on thick copper substrates. The pre-bake treatment was performed at 180 °C for 1 h. In tests conducted at 85 °C/85% relative humidity and ambient atmosphere, whisker formation was suppressed considerably when a pre-bake treatment was applied. After the pre-bake treatment, Cu3Sn intermetallic compounds were formed at the tin-copper interface. Cu3Sn IMCs play an important role in the formation of regular-shaped Cu6Sn5. Cu3Sn IMCs were also formed after temperature cycling and under conditions of 85 °C/85% RH. Irregular-shaped Cu6Sn5 IMCs were formed under all test conditions except for pre-baked samples in ambient atmosphere. A pre-bake treatment at 180 °C is advantageous for the inhibition of whisker formation and allows for planar and regular-shaped Cu3Sn to be produced.

Experimental study of bump void formation according to process conditions

Abstract Experimental studies of void formation were performed using a solder paste with a small particle size and a thin substrate with a small solder resist opening (SRO) size. Two kinds of Sn–Ag–Cu solder paste, screen printing mask opening (MO) size and pad finishes, and three kinds of SRO sizes were used as process variables. In this study, paste type and MO size had little influence on the formation of voids. In general, fewer voids were formed using the electroless nickel electroless palladium immersion gold (ENEPIG) pad finish than the organic solderability preservative (OSP) pad finish. However, the suitability of the pad finish was different depending on the type of paste. Void formation reduced with decreasing SRO. Both focused ion beam cross-sectioning and a thermal video system were used to ascertain the mechanism of void formation when using the paste with a small particle size, and the entrapment of flux was identified as the main cause for the formation of voids.

Reliability Evaluation for a Wet-Plated Electrode with a Al/Al2O3/Cu Insulated Metal Substrate

The heat sink in LED chips has been a major challenge for high-power LED module design. Elevated chip temperatures cause adverse effects on LED performance, lifetime, and color. An insulated metal substrate (IMS) is the commonly used substrate and has good thermal performance and low cost. This study used an aluminum IMS with good heat radiation efficiency to solve these problems. The most traditional IMS technique is electrochemical anodization. There are various methods to form electrical conductors on anodized aluminum. In this study, the anodization process was performed on an aluminum substrate using a phosphoric acid electrolyte to form the AAO layer. This investigation confirmed that electroless Ni-P plating for seed layers could be used to substitute for the Cu-sputtering process. Our evaluation of the reliability of the different thicknesses of aluminium anodic oxidation and the electro-plated Cu electrode revealed that the maximum peel strength was 1.6 kgf/cm and it was obtained at an anodizing time of 1000 minutes. The TCT, the solder shock test and the solderability test showed that the substrates were not delaminated. †(Received October 15, 2012)

Electrical properties of a unique solid array capacitor with 6 capacitance consisting of 4 electrodes and 3 organic dielectrics in single body

We investigated the electrical properties of a unique solid array capacitor with 6 capacitances consisting of 4 electrodes and 3 organic dielectrics in single body. The unique solid array capacitors with 4 electrodes and 3 dielectrics were composed of Cu/organics Di-electric/Cu/organics Di-electric/Cu/organics Di-electric/Cu with horizontal arrays structure. It was made by a new and unique fabrication process. A 4 cu sheet and a 3 organic sheet are stacked up in a vertical direction. The stacked materials are then pressed vertically using temperature, pressure, and time. The pressed samples were mechanically cut into the designed sizes in the transverse and longitudinal directions. When the cutted sample is laid flat, a 4 cu electrode and 3 organic di-electrics can be made a unique solid array capacitor horizontally. A size of the completed array capacitor is 3x4.86x0.5mm and 2.7x3.6x0.5mm. The length of the electrode and organic Di-electric is about 0.5 mm at plane. The thickness of the fabricated array capacitor in the vertical direction is 0.5 mm. It has 6 capacitances with a series-type structure. The capacitance values calculated by the formula and the measured capacitance values were compared with each other. C1, C2, and C3 of Sample1 and Sample2 show that the difference between the calculated value and the measured value is as small as about 5% or less for a 0.349 pF of sample 1 and a 0.301 pF of sample 2. C4, C5, and C6 were compared within 13∼15% of the calculated and measured values. The variation of the measured capacitance was confirmed to be within 15%.We investigated the electrical properties of a unique solid array capacitor with 6 capacitances consisting of 4 electrodes and 3 organic dielectrics in single body. The unique solid array capacitors with 4 electrodes and 3 dielectrics were composed of Cu/organics Di-electric/Cu/organics Di-electric/Cu/organics Di-electric/Cu with horizontal arrays structure. It was made by a new and unique fabrication process. A 4 cu sheet and a 3 organic sheet are stacked up in a vertical direction. The stacked materials are then pressed vertically using temperature, pressure, and time. The pressed samples were mechanically cut into the designed sizes in the transverse and longitudinal directions. When the cutted sample is laid flat, a 4 cu electrode and 3 organic di-electrics can be made a unique solid array capacitor horizontally. A size of the completed array capacitor is 3x4.86x0.5mm and 2.7x3.6x0.5mm. The length of the electrode and organic Di-electric is about 0.5 mm at plane. The thickness of the fabricated array ...

VIA Reliability Evaluation of Embedded MLCC through Pressure Cooker Test

A via reliability test of PCB board using embedded MLCC was evaluated by HALT and Pressure Cooker Test PCT. The reliability of HALT was evaluated at 125 , 4Vr, and 12Hr. The purpose of this test was to verify the stability of the MLCC by predicting the lifetime of the PCB. The PCBT conditions were measured at 85% humidity and 2 atm, and the reliability of the PCBs under severe conditions than HALT was evaluated. The basic characteristics of MLCC size are 0603 (600x300um), Capacitance 100nF, thickness 150µm. The initial electrical characteristics of the MLCC size are 0603 (600 x 300 um), Capacitance 100 nF, thickness 150 um. The initial electrical characteristics of the MLCC were measured at a rated voltage (10V) with a capacitance value of 98 ~ 103 nF, a loss rate of 0.048%, and an insulation resistance of 1.08 x 1010 (omega). The HALT test results showed that all the measured samples showed a value of 1 x 107 (omega) or more, and passed for the HALT test. The PCBT test resulted in failure, and the first sample fell below the poor insulation resistance at the start of the PCBT test. In the case of the second sample, the insulation resistance dropped to less than the defective insulation resistance for more than 30 hours, and the third sample has an appropriate insulation resistance of 1.0x106 even for more than 60 hours. It is confirmed that there is the greatest the possibility of failure in the part between the embedded chip and via that Cu plating is performed to form via by fill plating. Therefore, it is necessary to optimize the plating thickness and size conditions because the embedded MLCC has a high probability that defects mainly occur in VIA crack or delamination