Seung-Kyu Lim

Fabrication of a Touch Sensor for Flat Panel Displays Using Poly(3,4-ethylenedioxythiophene):Poly(styrene sulfonate) with Dimethylsulfoxide by Soft Lithography

In this study, a transparent conductive-polymer-based sensor array designed for use in a touch screen panel was fabricated using soft lithography. One of the most promising conductive polymers, poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), was used as the conductive material, and the secondary dopant dimethyl sulfoxide (DMSO) was used to increase the conductivity. The experiments were conducted using various DMSO concentrations in PEDOT:PSS in order to identify the optimum conditions to achieve high conductivity and transmittance. The electrical properties of PEDOT:PSS thin films were investigated using a four-point probe, and their transmittance was determined using an UV–vis spectrometer. The surface morphology was observed by field emission scanning electron microscopy (FE-SEM) and atomic force microscopy (AFM). A stable conductivity in the range of 110–204 S/cm was obtained at 0–30% DMSO concentrations, and the transmittances were greater than 92% in the visible range.

Experimental study of bump void formation according to process conditions

Abstract Experimental studies of void formation were performed using a solder paste with a small particle size and a thin substrate with a small solder resist opening (SRO) size. Two kinds of Sn–Ag–Cu solder paste, screen printing mask opening (MO) size and pad finishes, and three kinds of SRO sizes were used as process variables. In this study, paste type and MO size had little influence on the formation of voids. In general, fewer voids were formed using the electroless nickel electroless palladium immersion gold (ENEPIG) pad finish than the organic solderability preservative (OSP) pad finish. However, the suitability of the pad finish was different depending on the type of paste. Void formation reduced with decreasing SRO. Both focused ion beam cross-sectioning and a thermal video system were used to ascertain the mechanism of void formation when using the paste with a small particle size, and the entrapment of flux was identified as the main cause for the formation of voids.

Silicon interposer BGA package with a Cu-filled through silicon via and a multilayer redistribution layer fabricated via electroplating.

As large-scale integrated circuit chips become smaller, conventional organic buildup substrates can no longer support them. To resolve this problem, silicon interposers with through silicon via (TSV) technology are gaining recognition as alternative solution to provide high-density interconnection, improved electrical performance due to shorter interconnection from the die to substrate for nano-scale devices. In this study, we fabricated a silicon interposer to achieve high density and high performance packages. Via holes were etched via the Bosch process using a deep reactive ion etcher and SiO2 formed with a diffusion furnace as the diffusion barrier of the Cu electrode. TSVs were filled with Cu under various electroplating conditions. After Cu filling, a Cu post was formed directly using the over-filled Cu electrode through a chemical mechanical polishing process. A double-layer redistribution layer was formed on one side of the interposer using a lift-off process. Sn-3.5% Ag solder bumps 40 μm in diameter were formed directly on the Cu post on another side of the interposer using electroplating and the reflow method.

Fabrication and Characteristics of Through Silicon Vias Interconnection by Electroplating

The electroplating method was improved using double anodes and a penetrated jig to fill high-aspect-ratio through silicon vias (TSVs) with copper. In this study, the double anodes were used to limit the formation of voids that degrade the electrical properties when the device is working. In addition, in this study we examined how the V-shaped electroplated copper is formed in the first electroplating step to seal openings. After establishing the conditions for electroplating using the double anodes and current wave, a void-free interconnection was fabricated, which consisted of TSVs with a diameter of 40 µm and an aspect ratios of 6.25:1 and 10:1 for silicon interposers.