Hwh Harmke de Groot

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s.

A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step

Applications like wireless sensor nodes require ultra-low-power ADCs. However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates. An efficiently scalable sample rate (10kS/s to 10MS/s) has been demonstrated before, but without scalability of resolution. In, an ADC with both flexible resolution and sample rate is reported; however, its power efficiency is not as good as the point-solutions in. This paper describes a SAR ADC that achieves both good power efficiency (6.5-to-16fJ/conversion-step) and a wide range of flexibility (7-to-10b resolution, sample rates up to 4MS/s) to cover a large variety of applications, thereby reducing cost, design-time and overall complexity. To optimize the power efficiency for each resolution, both the DAC and comparator are reconfigurable. A 2-step conversion scheme is proposed for 9 and 10b settings to further reduce the power consumption. Finally, the use of an asynchronous architecture and dynamic circuitry ensures that the power consumption scales inherently proportional to the sample rate.

A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios

This paper presents an 8-bit asynchronous SAR ADC for flexible, low energy radios. The prototype in a 90nm CMOS technology achieves an ENOB of 7.7bit at a sampling frequency of 10.24MS/s while consuming 26.3µW from a 1V supply. Excellent power efficiency is achieved by using asynchronous dynamic logic, custom 0.5fF unit capacitors, a low-complexity design and an optimized layout. The measured prototype achieves a FoM of 12fJ/conversion-step, which is a 2.5x improvement over previous state-of-the-art 8-bit converters. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6nW.

A 0dBm 10Mbps 2.4GHz ultra-low power ASK/OOK transmitter with digital pulse-shaping

This paper presents an ultra-low power transmitter used for wireless sensor network (WSN) and wireless body area network (WBAN) applications. The proposed 2.4GHz direct modulation transmitter radiates 1mW with 3.88mW power consumption, and it supports OOK and ASK modulation up to 10Mbps. The novel power amplifier structure enables digital pulse-shaping to improve spectrum efficiency of OOK transmission. When applied with OOK modulation with equal probability of 1s and 0s, it consumes 2.3mW with an energy efficiency of 0.23nJ/bit/mW. The transmitter is implemented in a 90nm CMOS technology and packaged in a QFN56 package.

A 0.47–1.6mW 5bit 0.5–1GS/s time-interleaved SAR ADC for low-power UWB radios

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

A 0.7V 7-to-10bit 0-to-2MS/s flexible SAR ADC for ultra low-power wireless sensor nodes

This paper presents a flexible SAR ADC in 90nm CMOS for wireless sensor nodes. By supporting resolutions from 7 to 10bit and sample rates from DC to 2MS/s, this design can be used for a variety of applications such as sensor interfacing and receiver frontends. Flexibility is achieved by a reconfigurable comparator and a reconfigurable DAC. Compared to prior art, this work substantially improves power-efficiency and enables low-voltage operation by employing a pseudo-differential DAC switching scheme, offset compensation and simplified asynchronous logic control. The measured chip achieves power-efficiencies of 2.8-6.6fJ/conversion-step at 2MS/s and 0.7V supply. The FOM is maintained down to kS/s-range as the leakage is only 2nW.

A 500mW 5Mbps ULP super-regenerative RF front-end

This paper presents an ultra low power superregenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36–2.4 GHz medical BAN and 2.4–2.485 GHz ISM bands, and consumes 500 mW. It supports OOK modulation at high data rates ranging from 1–5 Mbps. It achieves a sensitivity of −67 dBm at a BER of 10−3. The combination of digital and analog quench generation and RF front-end optimization provides ultra-low power consumption at high data rates. The RF front end is implemented in a 90 nm CMOS technology and is packaged in a QFN56 package.

10ns Start-up techniques for a duty cycled Impulse Radio receiver

This paper presents fast start-up techniques for duty cycled Impulse Radio receivers. Three different techniques are used to improve the start-up time of individual blocks. DC coupling between the mixer and the VGA is used to ensure a fast start-up time for the whole chain, resulting in an overall start-up time below 10ns. This is the fastest startup time reported for duty cycled Impulse Radio receivers. Moreover, to the best of our knowledge, this is the first paper to detail the start-up techniques that enable ultra-low power consumption in this class of receivers. The measured power consumption is scaling proportionally to the duty cycling rate from 46mW in continuous mode down to 58uW for <;0.01% duty cycle rate.

A 0.37μW 4bit 1MS/s SAR ADC for ultra-low energy radios

This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37μW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.

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A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them simultaneously in a stepwise feedback loop. The calibration achieves 20 dB spur reduction with little area and power overhead. The chip is implemented in 40 nm CMOS and consumes 46