Pja Pieter Harpe

A

This paper presents an active electrode system for gel-free biopotential EEG signal acquisition. The system consists of front-end chopper amplifiers and a back-end common-mode feedback (CMFB) circuit. The front-end AC-coupled chopper amplifier employs input impedance boosting and digitally-assisted offset trimming. The former increases the input impedance of the active electrode to 2 GΩ at 1 Hz and the latter limits the chopping induced output ripple and residual offset to 2 mV and 20 mV, respectively. Thanks to chopper stabilization, the active electrode achieves 0.8 μVrms (0.5-100 Hz) input referred noise. The use of a back-end CMFB circuit further improves the CMRR of the active electrode readout to 82 dB at 50 Hz. Both front-end and back-end circuits are implemented in a 0.18 μm CMOS process and the total current consumption of an 8-channel readout system is 88 μA from 1.8 V supply. EEG measurements using the proposed active electrode system demonstrate its benefits compared to passive electrode systems, namely reduced sensitivity to cable motion artifacts and mains interference.

160~\mu {\rm W}

This paper presents a multistandard ultra-low-power (ULP) 2.36/2.4GHz transceiver for personal and body-area networks (PAN/BAN). The presented radio complies with 3 short-range standards: Bluetooth Low Energy (BT-LE), IEEE802.15.4 (ZigBee) and IEEE802.15.6 (Medical Body-Area Networks, MBAN). A proprietary 2Mb/s mode is also implemented to support data-streaming applications like hearing aids. Current short-range radios for Zigbee and BT-LE typically consume more than 20mW DC power, which is rather high for autonomous systems with limited battery energy. The dual-mode MBAN/BT-LE transceiver achieves a power consumption of 6.5mW for the RX and 5.9mW for the TX by employing a sliding-IF RX and a polar TX architecture. However, it suffers from limited RX image rejection and needs a PA operating at a higher supply voltage. In this paper, an energy-efficient radio architecture with a suitable LO frequency plan is selected, and several efficiency-enhancement techniques for the critical RF circuits (e.g., a push-pull mixer and a digitally-assisted PA) are utilized. As a result, the presented transceiver dissipates only 3.8mW (RX) and 4.6mW (TX) DC power from a 1.2V supply, while exceeding all of the PHY requirements of above 3 standards.

8-Channel Active Electrode System for EEG Monitoring

Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s.

A 1.9nJ/b 2.4GHz multistandard (Bluetooth Low Energy/Zigbee/IEEE802.15.6) transceiver for personal/body-area networks

Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environmental information, or interactive multimedia. For these applications, state-of-the-art SAR ADCs can provide highly power-efficient solutions (<;10fJ/conversion-step) but with limited accuracy (SNDR <;63dB) [1,2]. Alternatively, ΔΣ ADCs offer higher precision at the cost of lower efficiency (e.g. 84dB SNDR with 54fJ/conversion-step [3]). This work bridges the existing performance gap by extending the accuracy of low-power SAR ADCs to SNDRs in the order of 70-to-80dB. Feedback-controlled data-driven noise reduction [1], oversampling, chopping [4] and dithering [5] techniques are combined to increase both SNR and linearity in a power-efficient way. Various ADC modes are supported by making these techniques individually programmable, thereby extending the application range.

A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction

This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.

11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR

Applications like wireless sensor nodes require ultra-low-power ADCs. However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates. An efficiently scalable sample rate (10kS/s to 10MS/s) has been demonstrated before, but without scalability of resolution. In, an ADC with both flexible resolution and sample rate is reported; however, its power efficiency is not as good as the point-solutions in. This paper describes a SAR ADC that achieves both good power efficiency (6.5-to-16fJ/conversion-step) and a wide range of flexibility (7-to-10b resolution, sample rates up to 4MS/s) to cover a large variety of applications, thereby reducing cost, design-time and overall complexity. To optimize the power efficiency for each resolution, both the DAC and comparator are reconfigurable. A 2-step conversion scheme is proposed for 9 and 10b settings to further reduce the power consumption. Finally, the use of an asynchronous architecture and dynamic circuitry ensures that the power consumption scales inherently proportional to the sample rate.

A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step

This paper presents a low-voltage current-reuse chopper-stabilized frontend amplifier for fetal ECG monitoring. The proposed amplifier allows for individual tuning of the noise in each measurement channel, minimizing the total power consumption while satisfying all application requirements. The low-voltage current reuse topology exploits power optimization in both the current and the voltage domain, exploiting multiple supply voltages (0.3, 0.6 and 1.2 V). The power management circuitry providing the different supplies is optimized for high efficiency (peak charge-pump efficiency = 90%).The low-voltage amplifier together with its power management circuitry is implemented in a standard 0.18 μm CMOS process and characterized experimentally. The amplifier core achieves both good noise efficiency factor (NEF=1.74) and power efficiency factor (PEF=1.05). Experiments show that the amplifier core can provide a noise level of 0.34 μVrms in a 0.7 to 182 Hz band, consuming 1.17 μW power. The amplifier together with its power management circuitry consumes 1.56 μW, achieving a PEF of 1.41. The amplifier is also validated with adult ECG and pre-recorded fetal ECG measurements.

A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step

A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. The complete, duty-cycled transmitter provides +1dBm peak output power, consuming 4.4mW. The receiver front-end shows −88dBm sensitivity at 0.85Mbps and a digital synchronization algorithm enables real-time duty cycling, resulting in a mean power consumption of 3mW.

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400 aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90 nm CMOS occupies only 0.11 mm2 including decoupling capacitors. Two relevant modes for UWB are supported: 0.5 GS/s at 0.75 V supply, and 1 GS/s at 1 V supply with 0.47 mW and 1.6 mW power consumption respectively. With an ENOB of 4.7 and 4.8 bits, this leads to energy efficiencies of 36 and 57 fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.