Hyeokjong Lee

A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM

This paper presents an ultra-low-power singlechip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 × 1.7 mm2 in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34µW under a network environment.

A Low-Power Multi Resolution Spectrum Sensing (MRSS) Architecture for a Wireless Sensor Network with Cognitive Radio

Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW.

A 40-nm 640-µm 2 45-dB opampless all-digital second-order MASH ΔΣ ADC

This paper presents a second-order ΔΣ analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moores law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 µW. Its area is 640 µm2.

A 60-dB image rejection filter using Δ-Σ modulation and frequency shifting

We propose a novel image rejection scheme for a low-IF (low intermediate frequency) receiver. A Δ-Σ modulator converts I/Q signals to digital values, and then they are digitally processed. The Δ-Σ modulator is a second-order complex band-pass type; the proposed architecture is suitable for various multi-channel communications and/or cognitive radio. As the first step in the digital signal processing, a spectrum is shifted so that the desired signal band is centered at 0 Hz. Next, by LPFs (low-pass filters), an image signal and the quantization noise of the Δ-Σ modulator are removed. These LPFs also function as a decimation filter; thus a dedicated decimation filter is not needed, and an extra area and power for it are saved. The test chip occupies 0.75 mm2 in a 180-nm mixed-signal process. The power is 6.0 mW at 1.8 V. The IRR (image rejection ratio) achieves 60 dB.

A flexible baseband processor with multi-resolution spectrum-sensing functionality

In this paper, we propose a reconfigurable baseband processor for a cognitive radio that has multi-resolution bandpass filters. By applying the distributed arithmetic algorithm to the reconfigurable baseband processor and rewriting SRAM data in it, a channel center frequency and bandwidth are reconfigurable. The filter bandwidth can be changed from 40 kHz to 240 kHz with a 10 kHz resolution on our prototype processor. The power is 13 mW at a supply voltage of 1.8 V in a 0.18-mum CMOS process.