Shintaro Izumi

Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection

This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 × 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 ~ 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a high-resolution camera and higher operating frequency are available.

A Wearable Healthcare System With a 13.7

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

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In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented. The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. Early classification reduces the number of computations in SVM classification. The dual core architecture and the detection-window-size scalable architecture enable the processor to operate in several modes: high-speed mode, low-power mode, multiple object detection mode, and multiple shape object detection mode. These techniques expand the processor flexibility required for versatile application. The test chip was fabricated using 65 nm CMOS technology. The proposed architecture is designed to process HDTV resolution video (1920 × 1080 pixels) at 30 frames per second (fps). The performance of this accelerator is demonstrated on a pedestrian detection system.

A Noise Tolerant ECG Processor

This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. Simulation results show that the proposed method improves the success rate of IHR detection by up to 37%.

A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection

We have been developing a hands-free voice controller for a home network system (HNS) by using microphone arrays. In our current implementation, however, all human-HNS interactions are performed by voice only. Hence, the interactions tend to be mechanical, dreary and uninformative. To achieve richer interactions, we try to introduce the virtual agent technology as a feedback interface of the HNS. In this paper, we implement the virtual agent as a Web service, by using MMDAgent Toolkit extensively. The agent is then integrated with the HNS and microphone arrays in a service-oriented fashion. Finally, we conduct a user experiment with three versions of virtual agents. In the experiment, we evaluate how the virtual agent can enrich the interactions.

Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems

This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μA including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.

Implementing Virtual Agent as an Interface for Smart Home Voice Control

This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector

This paper presents an ultra-low-power singlechip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 × 1.7 mm2 in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34µW under a network environment.

A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system

This paper describes a robust method for heart beat detection from noisy electrocardiogram (ECG) signals. Generally, the QRS-complex of heart beat is extracted from the ECG using a threshold. However, in a noisy condition such a mobile and wearable bio-signal monitoring system, noise increases the incidence of misdetection and false detection of QRS-complex. To prevent incorrect detection, we introduce a novel template matching algorithm. The template waveform can be generated autonomously using a short-term autocorrelation method, which leverages the similarity of QRS-complex waveforms. Simulation results show the proposed method achieves state-of-the-art noise tolerance of heart beat detection.

A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM

This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.