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Dive into the research topics where Hyuck-Jin Kang is active.

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Featured researches published by Hyuck-Jin Kang.


international symposium on semiconductor manufacturing | 2005

Study on reliability of metal fuse for sub-100nm technology

Don Park; Chang-Suk Hyun; Hyun-Chul Kim; Hyuck-Jin Kang; Kang-yoon Lee; Kyung-seok Oh

Tungsten bit line fuse has been used for years in repair application but it fails during BOC (board on chip) package PCT (pressure cooker test) because of its weakness to corrosion. We searched for new material against corrosion, and metal-1 aluminum fuse was set up. Although there is no failure in PCT, we have found a fatal failure in IMD (inter-metal dielectric) crack during THB (temperature humidity bias test). We developed SiN full passivation scheme to resolve the failure then there is no failure until THB 1000 hours. Finally we set up metal-1 aluminum fuse process for sub-100 nm technology


Japanese Journal of Applied Physics | 2005

Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide

Seong-Goo Kim; Chang-Suk Hyun; Don Park; Tai-heui Cho; Hong-Joon Moon; Hyunchul Kim; Jae-Hwang Jung; Sun-Joon Kim; Hyuck-Jin Kang; Sang-Moo Jeong; Si-Woo Lee; Sung-Hyun Lee; Jong-Gyu Suk; Young-Soo Jeon; Sang-Kil Jeon; Hyeong-Sun Hong; Kang-yoon Lee; Kyung-seok Oh

In this paper the novel robust Hemispherical Grain (HSG)-merged Al2O3/HfO2 (AHO) capacitor with diagonal cell array scheme and double mold oxide (DMO) is introduced. The capacitor process with diagonal cell array scheme and double mold oxide can maximize storage node (SN) height up to 2.0 µm in 0.11 µm dynamic random access memory (DRAM) technology by enlarging the bottom size of SN. Also we developed the HSG-merged AHO capacitor for the first time in mass production. The HSG-merged AHO capacitor technique exhibited a capacitance enhancement by 24% without any significant decrease in breakdown voltage compared to Al2O3 (ALO) capacitor.


Archive | 2004

Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same

Tai-heui Cho; Hyuck-Jin Kang; Heui-Won Shin; Gwang-Seon Byun; Sun-Joon Kim


Archive | 2002

Semiconductor device having a contact window and fabrication method thereof

Hyuck-Jin Kang; Tai-heui Cho


Archive | 2003

Bonding pad structure of a semiconductor device and method for manufacturing the same

Tai-heui Cho; Hyuck-Jin Kang; Min-Chul Kim; Byung-Yoon Kim


Archive | 2002

Bonding pad structure for semiconductor device and manufacturing method therefor

Tai-heui Cho; Hyuck-Jin Kang; Byung-Yoon Kim; Min-Chul Kim; 赫鎮 姜; 太煕 趙; ▲ミン▼▲チュル▼ 金


Archive | 2002

Bonding pad structure of a semiconductor device

Tai-heui Cho; Hyuck-Jin Kang; Min-Chul Kim; Byung-Yoon Kim


Archive | 2005

Fuse region of a semiconductor device and method of fabricating the same

Hyuck-Jin Kang; Chang-Suk Hyun; Il-Young Moon; Kang-yoon Lee; Kwang-bo Sim; Sang-Kil Jeon


Archive | 2005

Fuse region of a semiconductor region

Hyuck-Jin Kang; Chang-Suk Hyun; Il-Young Moon; Kang-yoon Lee; Kwang-bo Sim; Sang-Kil Jeon


Archive | 2002

Bonding pad structure for semiconductor integrated circuit, comprises bonding pad having first and second interconnection layers integral to each other, and peg(s) integral with the bonding pad

Tae-Heui Cho; Hyuck-Jin Kang; Min-Chul Kim; Byung-Yoon Kim

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