Kyung-seok Oh

55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure.

Study on reliability of metal fuse for sub-100nm technology

Tungsten bit line fuse has been used for years in repair application but it fails during BOC (board on chip) package PCT (pressure cooker test) because of its weakness to corrosion. We searched for new material against corrosion, and metal-1 aluminum fuse was set up. Although there is no failure in PCT, we have found a fatal failure in IMD (inter-metal dielectric) crack during THB (temperature humidity bias test). We developed SiN full passivation scheme to resolve the failure then there is no failure until THB 1000 hours. Finally we set up metal-1 aluminum fuse process for sub-100 nm technology

Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices

High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40∼60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Mobile DRAM is widely adopted in battery-powered portable devices because of its low power. Recently, in mobile devices such as smart phones and tablet PCs, higher performance is required to support 3D gaming mode and high-quality video. These trends lead to consideration of higher-performance DRAMs than LPDDR2, while the power budget for DRAMs for mobile devices cannot increase. DRAMs with wide I/O or serial I/O have been reviewed as candidates for over 6.4GB/s channel bandwidth. However, wide-I/O DRAMs [1] must solve issues such as stacking yield for higher density and failure analysis modeling of system-in-package (SiP), and most serial I/Os have worse I/O power efficiency than LPDDR2. For an evolutionary successor of LPDDR2, therefore, we design a 1.2V 1.6Gb/s/pin ×32 4Gb low-power DDR3 SDRAM (LPDDR3) with input skew calibration and enhanced refresh control schemes, achieving 6.4GB/s total data bandwidth. Most features of LPDDR3 are backward compatible with LPDDR2, except that channel termination, command-address (CA) training, and write leveling are adopted.

A 31 ns Random Cycle VCAT-Based 4F

A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F2 cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F2 DRAM.

^{2}

We studied random telegraph noise (RTN) of n-type and p-type silicon nanowire transistors (SNWT) for the first time and derived accurate vertical and lateral trap location equations in nanowire structure. Using the derived equations, accurate trap locations were extracted in the devices with single trap as well as multiple traps.

DRAM With Manufacturability and Enhanced Cell Efficiency

We present R-SOAs with improved modulation bandwidth of /spl sim/1.35 GHz as WDM sources in 1.25 Gbit/s WDM-PONs. In back-to-back transmission using the R-SOA seeded by 0.6 nm-wide ASE of -20 dBm, receiver sensitivity at a 10/sup -9 /BER was - 25.3 dBm.

Random Telegraph Noise in n-type and p-type silicon nanowire transistors

In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at off current of 1nA/mum for NMOS and PMOS, respectively.

Reflective SOAs optimized for 1.25 Gbit/s WDM-PONs

In this paper the novel robust Hemispherical Grain (HSG)-merged Al2O3/HfO2 (AHO) capacitor with diagonal cell array scheme and double mold oxide (DMO) is introduced. The capacitor process with diagonal cell array scheme and double mold oxide can maximize storage node (SN) height up to 2.0 µm in 0.11 µm dynamic random access memory (DRAM) technology by enlarging the bottom size of SN. Also we developed the HSG-merged AHO capacitor for the first time in mass production. The HSG-merged AHO capacitor technique exhibited a capacitance enhancement by 24% without any significant decrease in breakdown voltage compared to Al2O3 (ALO) capacitor.

Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

For the first time, we have analyzed low frequency noise (1/f) of p-type silicon nanowire transistors (SNWT), and investigated its bias dependency. The results were compared with those in n-type silicon nanowire transistors as well as planar MOSFETs.