Thomas Moon

Through-silicon-via management during 3D physical design: when to add and how many?

In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods.

Wideband Sparse Signal Acquisition With Dual-rate Time-Interleaved Undersampling Hardware and Multicoset Signal Reconstruction Algorithms

A new undersampling-based dual-rate signal acquisition technique for measuring a wideband sparse signal (i.e., a multiband signal) is presented in this paper. The proposed architecture employs a combination of dual-rate time-interleaved undersampling hardware and associated multicoset back-end signal processing algorithms. In dual-rate sampling hardware, a pair of uniform samplers is used to acquire a common incoming wideband sparse signal while the operation frequencies of the two samplers have a small frequency offset. Due to the sampling frequency offset, the time grids of the samples obtained from the two samplers are irregularly spaced. These nonuniform periodic samples are then digitally re-sequenced and applied as input to a multicoset signal reconstruction algorithm. The multicoset signal reconstruction algorithm uses the re-sequenced nonuniform periodic samples to achieve a perfect reconstruction of the original wideband signal with an enhanced time resolution beyond the sampling hardwares capability. Compared to the conventional multi-channel sampling approach commonly used with multicoset algorithms, the proposed method uses fewer sampling channels and does not require their accurate clock phase adjustment.

Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noise

In this paper, we propose a wideband signal reconstruction scheme for testing high-speed pseudo random bit sequences (PRBSs) in the presence of jitter noise using incoherent sampling. The proposed approach exploits synchronous multirate sampling (SMRS) hardware and multicoset back-end signal processing algorithms. The SMRS hardware consists of multiple analog-to-digital converters (ADCs) whose sampling frequencies are synchronized with a common frequency reference and can be individually configured. The optimal sampling frequency of each ADC is chosen based on the input signal information and sampling hardware specifications. As compared to other sampling hardware used for multicoset signal reconstruction, the proposed approach uses less number of ADCs and does not require accurate sampling clock phase adjustment. In the digital signal reconstruction, the input waveform is reconstructed by the multicoset signal processing algorithms and the phase noise of each tone of the PRBS test signal is measured.

Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware

Characterizing the spectrum of sparse wideband signals of high-speed devices efficiently and precisely is critical in high-speed test instrumentation design. Recently proposed sub-Nyquist rate sampling systems have the potential to significantly reduce the cost and complexity of sparse spectrum characterization; however, due to imperfections and variations in hardware design, numerous implementation and calibration issues have risen and need to be solved for robust and stable signal acquisition. In this paper, we propose a low-cost and low-complexity hardware architecture and associated asynchronous multi-rate sub-Nyquist rate sampling based algorithms for sparse spectrum characterization. The proposed scheme can be implemented with a single ADC or with multiple ADCs as in multi-channel or band-interleaved sensing architectures. Compared to other sub-Nyquist rate sampling methods, the proposed hardware scheme can achieve wideband sparse spectrum characterization with minimum cost and calibration effort. A hardware prototype built using off-the-shelf components is used to demonstrate the feasibility of the proposed approach.

Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters

In this paper, a higher than Nyquist RF test waveform synthesizer with digital phase noise injection is proposed. The proposed system uses time-interleaved digital-to-analog converters (DACs) and associated digital signal processing algorithms to enhance the spectral image of the synthesized waveform in the high-order Nyquist zones by increasing the effective sampling rate and eliminating unwanted signals inside the bandwidth of interest. The generated spectral images are used as the primary output of the proposed system. The waveform synthesizer is capable of digitally controlling the phase noise characteristics of the output signal in the high-order Nyquist zones. In addition, it utilizes relatively low-cost off-the-shelf integrated circuits (ICs) for multi-GHz signal generation. In hardware validation, dual DACs operating at 2.5Gb/s (effective Nyquist rate of 5 Gb/s) are used to generate a signal centered at 3.2GHz (corresponding to a Nyquist rate of 6.4 GHz). In addition, controlled phase noise generation is demonstrated.

An FPGA-based ATE extension module for low-cost multi-GHz memory test

This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost “host” test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel “pin electronics” (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and pre-emphasis, and a “shadow sampler.”

Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling

In this paper, we propose a new algorithm to estimate the fundamental period (frequency) of a highspeed pseudo random bit sequence (PRBS) or multitone signal using incoherent subsampling. While incoherent subsampling suffers from spectral leakage due to the mismatch between the input test signal and the discrete Fourier transform (DFT) basis, the proposed algorithm efficiently resolves the spectral leakage problem using a back-end signal process. The approach requires incoherent digitization of the periodic sequence using at least two clocks running at different speeds. No additional hardware to synchronize the input signal frequency with the sampling clock frequency is needed. A new discrete frequency shifting approach for determining the period of the input signal is proposed that is computationally efficient. The signal reconstruction approach has been tested with experimental results.

Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms

This paper proposes a new multi-channel testing architecture for high-speed eye-diagram. The proposed architecture reconstructs the eye-diagram of a multi-Gbps bit pattern with the combination of pin electronics and reconstruction algorithms. A scalability of the test system significantly increases in behalf of a monobit receiver and its designated reconstruction algorithm. A novel reconstruction algorithm using monobit receiver and subsampling clock enables the test system to monitor the signal quality in low-cost. The proposed architecture is implemented and demonstrated in a hardware prototype. Experiment with the hardware prototype shows that an eye-diagram of 3.2Gbps bit pattern can be reconstructed within sub-picosecond resolution by the proposed method with subsampling clock (below 100MHz).

Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution

In this paper, we propose a new test response acquisition technique for high-speed devices-based on dual-frequency incoherent sub-sampling and sparse signal reconstruction. The proposed technique enables reconstruction of spectrally sparse wideband signals such as multi-tone signals and short pseudo-random bit sequences (PRBS) with enhanced time/frequency resolution as opposed to current methods. The sampling hardware utilizes dual analog-to-digital converters (ADCs) and dedicated sampling frequency synthesizers with a common frequency reference. As compared to other compressive sampling architectures [1], the proposed hardware architecture is easy to implement at low cost since it does not require accurate sampling clock phase adjustment or random timing generation. For digital signal reconstruction, the proposed technique requires less number of waveform samples than conventional equivalent-time sampling techniques. In addition, the use of an resolution-enhanced discrete Fourier transform (DFT) frame and basis pursuit algorithms minimizes spectral leakage of incoherently sub-sampled signals. This co-design of sampling hardware and signal reconstruction algorithms enables testing of spectrally sparse wideband signals with enhanced time/frequency resolution.

Timing Noise Characterization of High-Speed Digital Bit Sequences Using Incoherent Subsampling and Algorithmic Clock Recovery

In this paper, we exploit a software-based nonreal-time signal acquisition technique to enable high-precision jitter characterization of multi-Gb/s pseudorandom bit sequences (PRBSs) with minimal hardware support. For signal acquisition, incoherent subsampling is employed to increase the effective sampling rate of a digitizer and to simplify its signal acquisition architecture by removing the need for timing synchronization circuits. As a substitute for hardware synchronization circuits, the multiple stages of discrete frequency estimation algorithm, called algorithmic clock recovery (CR), are used. Using the frequency estimate obtained from the proposed algorithmic CR allows us to digitally reconstruct an incoherently subsampled PRBS into a single period of the signal in the discrete-time-domain. The proposed algorithmic CR is accurate and robust, especially in the presence of signal noise and multiple aliased distortions as compared with previously published approaches. In addition, the proposed all-digital jitter characterization technique (including self-reference signal extraction) enables data-dependent jitter separation without using the tail-fitting of a jitter histogram.