Hyundoek Yang

Ti gate compatible with atomic-layer-deposited HfO2 for n-type metal-oxide-semiconductor devices

The electrical characteristics were evaluated for the metal-oxide-semiconductor (MOS) devices with Ti and Pt gates on the atomic-layer-deposited (ALD) HfO2. The equivalent oxide thickness (EOT) of the Ti gate is shown to be nearly the same as that of the Pt gate, which means that a negligible chemical reaction occurs between the gate and dielectric. The values of the effective metal work function (Φm,eff), extracted from the conventional relations of flatband voltage versus EOT, were ∼4.2eV for Ti and ∼5.4eV for Pt, respectively. However, somewhat higher values of Φm,eff were extracted by considering the existence of an interfacial layer and the high negative charge at an interface between HfO2 and interfacial layer. The exact values of Φm,eff were ∼4.37eV for Ti and ∼5.51eV for Pt, respectively. Therefore, the Ti gate is compatible with ALD-HfO2 and can be a candidate for n-type MOS devices.

Excellent electrical characteristics of lanthanide (Pr, Nd, Sm, Gd, and Dy) oxide and lanthanide-doped oxide for MOS gate dielectric applications

In this paper, we report on an investigation of the electrical characteristics of various amorphous lanthanide oxides prepared by e-beam evaporation. Excellent electrical characteristics were found for the amorphous lanthanide oxide including a high oxide capacitance, low leakage current, and high thermal stability. We also confirmed the excellent thermal stability and mobility characteristics of lanthanide silicate (PrSi/sub x/O/sub y/). In addition, lanthanide-doped HfO/sub 2/ also exhibited a significant reduction in leakage current at the same equivalent oxide thickness.

Improved Conductance Method for Determining Interface Trap Density of Metal–Oxide–Semiconductor Device with High Series Resistance

The existence of series resistance in metal–oxide–semiconductor (MOS) devices can result in both the degradation of capacitance at a high frequency and the decrease in conductance. Using a conventional conductance method that does not consider the series resistance, the interface trap density can be underestimated. We propose an improved conductance method based on an equivalent circuit model including the series resistance. Compared with the conventional method, this new method enables the accurate determination of interface trap density.

Ultralow work function of scandium metal gate with tantalum nitride interface layer for n-channel metal oxide semiconductor application

The authors have investigated n-channel metal oxide semiconductor compatible metal gate with ultralow work function using tantalum nitride (TaNx)/scandium(Sc) stack layer. By adjusting the deposition condition, the effective work function as low as 4.0eV with improved thermal stability can be obtained. Without TaNx layer, work function of pure Sc gate on HfO2 was about 4.2eV and show thermal instability at high temperature which can be explained by reaction between Sc and HfO2. The authors found that control of TaNx layer is the critical process to maintain thermal stability and work function. The TaNx∕Sc stack process shows promise for future high-k metal gate applications.The authors have investigated n-channel metal oxide semiconductor compatible metal gate with ultralow work function using tantalum nitride (TaNx)/scandium(Sc) stack layer. By adjusting the deposition condition, the effective work function as low as 4.0eV with improved thermal stability can be obtained. Without TaNx layer, work function of pure Sc gate on HfO2 was about 4.2eV and show thermal instability at high temperature which can be explained by reaction between Sc and HfO2. The authors found that control of TaNx layer is the critical process to maintain thermal stability and work function. The TaNx∕Sc stack process shows promise for future high-k metal gate applications.

Electrical and structural properties of nanolaminate (Al2O3/ZrO2/Al2O3) for metal oxide semiconductor gate dielectric applications

We investigated electrical and material properties of an untrathin nanolaminate (Al2O3/ZrO2/Al2O3) structure, prepared by atomic-layer chemical vapor deposition (ALCVD), for use in metal-oxide-semiconductor gate dielectric applications. The properties of nanolaminate were characterized by various technique such as high-resolution transmission electron microscopy (HRTEM), medium-energy ion scattering (MEIS), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and electrical analysis of MOS capacitors. Compared with the roughness of ZrO2 on bare silicon, ZrO2 on Al2O3 shows negligible roughness confirmed by AFM and HRTEM. Excellent electrical characteristics such as an equivalent oxide thickness (EOT) of 10.2 A and a leakage current density of 3×10-4 A/cm2 were obtained at 1 V below the flatband voltage. The conduction mechanism of nanolaminate can be explained by trap-assisted tunneling through ZrO2 and direct tunneling through Al2O3.

Ultrathin nitrided-nanolaminate (Al2O3/ZrO2/Al2O3) for metal–oxide–semiconductor gate dielectric applications

An ultrathin nanolaminate (Al2O3/ZrO2/Al2O3) film prepared by atomic layer chemical vapor deposition was investigated for use in metal–oxide–semiconductor field effect transistor (MOSFET) gate dielectric applications. Based on transmission electron microscopy and medium-energy ion scattering spectroscopy (MEIS) analysis, an abrupt interface between stoichiometric top-layer Al2O3 and ZrO2 was found. Interfacial layers such as Zr–Al–O and Al–Si–O were also observed. An electrical equivalent oxide thickness as thin as 10.2 A with a quantum mechanical correction was obtained. Additional plasma nitridation of nanolaminte in N2 led to a significant reduction in the interfacial oxidation of nanolaminate which was confirmed by x-ray photoelectron spectroscopy, MEIS, and capacitance–voltage (C–V) analysis. The nanolaminate film represents a promising alternative for gate dielectric applications of future sub-100 nm MOSFET.

Effect of Si lattice strain on the reliability characteristics of ultrathin SiO2 on a 4° tilted wafer

The electrical and structural characteristics of an ultrathin gate dielectric, thermally grown on 4° tilted wafer has been investigated. Compared with a control wafer, a relaxation of the Si lattice strain at the SiO2/Si(001) interface was observed for the 4° tilted wafer, which was confirmed by medium energy ion scattering spectroscopy. A significant improvement in the reliability characteristics of a metal–oxide–semiconductor (MOS) capacitor, with a 2.5-nm-thick gate oxide, grown on a tilt wafer was observed. This improvement in reliability can be explained by the relaxation of strain at the SiO2/Si interface. An ultrathin gate dielectric grown on a tilt wafer represents a promising alternative for gate dielectric applications in future MOS devices.

Effective Metal Work Function of High-Pressure Hydrogen Postannealed Pt–Er Alloy Metal Gate on HfO2 Film

We have investigated the effect of high-pressure hydrogen postannealing (HPHA) on the effective metal work function (Φm,eff) of a Pt–Er alloy metal gate on a HfO2 film. By considering the presence of an interfacial layer (IL) between the HfO2 film and a Si substrate and a negative charge at the HfO2/IL interface, the Φm,eff values of the Pt–Er alloy metal gate before and after HPHA, extracted from the relations of equivalent oxide thickness versus flat-band voltage, are determined to be ~5.1 and ~4.8 eV, respectively. The increase in the density of interface dipole caused by the reduction of PtOx during HPHA could be responsible for the decrease in Φm,eff.

Electrical characteristics of a TaOxNy/ZrSixOy stack gate dielectric for metal–oxide–semiconductor device applications

In this letter, we describe a process for the preparation of high-quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional chemical oxide and nitride as interfacial layers, TaOxNy metal–oxide–semiconductor capacitors using ZrSixOy as an interfacial layer exhibit lower leakage current levels at the same oxide thickness and a lower interface state density. We were able to confirm the TaOxNy/ZrSixOy stack structure by Auger electron spectroscopy and transmission electron microscopy analyses. Zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.