Kiju Im

Electron beam lithography patterning of sub-10nm line using hydrogen silsesquioxane for nanoscale device applications

We investigated novel patterning techniques to produce ultrafine patterns for nanoscale devices. Hydrogen silsesquioxane (HSQ) was employed as a high-resolution negative tone inorganic electron beam resist. The nanoscale patterns with sub-10nm linewidth were successfully formed. A trimming process of HSQ by the reactive ion etcher (RIE) played an important role for the formation of 5nm nanowire patterns. Additionally, hybrid lithography was used to produce various device patterns as well as to minimize proximity effects of electron beam lithography (EBL). Finally, we successfully fabricated triple-gate metal oxide semiconductor field effect transistor (MOSFET) with a gate length of 6nm by using the proposed patterning process.

Electrical characteristics of an ultrathin (1.6 nm) TaOxNy gate dielectric

This letter describes a process for the preparation of high-quality tantalum oxynitride (TaOxNy) via NH3 annealing of Ta2O5, for use in gate dielectric applications. Compared with tantalum oxide (Ta2O5), a significant improvement in the dielectric constant was obtained by the NH3 treatment. In addition, light reoxidation in a wet ambient at 450 °C resulted in a significantly reduced leakage current. We confirmed nitrogen incorporation in the tantalum oxynitride (TaOxNy) by Auger electron spectroscopy. By optimizing the nitridation and reoxidation processes, we obtained an equivalent oxide thickness as thin as 1.6 nm and a leakage current of less than 10 mA/cm2 at −1.5 V.

Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.

Excellent electrical characteristics of lanthanide (Pr, Nd, Sm, Gd, and Dy) oxide and lanthanide-doped oxide for MOS gate dielectric applications

In this paper, we report on an investigation of the electrical characteristics of various amorphous lanthanide oxides prepared by e-beam evaporation. Excellent electrical characteristics were found for the amorphous lanthanide oxide including a high oxide capacitance, low leakage current, and high thermal stability. We also confirmed the excellent thermal stability and mobility characteristics of lanthanide silicate (PrSi/sub x/O/sub y/). In addition, lanthanide-doped HfO/sub 2/ also exhibited a significant reduction in leakage current at the same equivalent oxide thickness.

Fabrication of fin field-effect transistor silicon nanocrystal floating gate memory using photochemical vapor deposition

The fin field-effect transistor (FET) silicon nanocrystal floating gate memory using the photochemical vapor deposition and the plasma doping processes was proposed. The silicon nanocrystals with a uniform size were formed on a vertical sidewall surface of the fin channel by the photochemical vapor deposition. The plasma doping was applied to form the junctions at the sidewall of the fin source-drain extension regions with a high aspect ratio. The FinFET silicon nanocrystal floating gate memory with a gate length of 100nm was successfully fabricated and it revealed a memory effect as well as a suppressed short-channel effect.

Electrical and reliability characteristics of an ultrathin TaO x N y gate dielectric prepared by ND 3 annealing of Ta 2 O 5

This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaO/sub x/N/sub y/) via the ND/sub 3/ annealing of Ta/sub 2/O/sub 5/, for use in gate dielectric applications. Compared with tantalum oxide (Ta/sub 2/O/sub 5/), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We were able to confirm nitrogen incorporation in the tantalum oxynitride (TaO/sub x/N/sub y/) by Auger electron spectroscopy. Compared with NH/sub 3/ nitridation, tantalum oxynitride prepared by nitridation in ND/sub 3/ shows less charge trapping and larger charge-to-breakdown characteristics.This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaO/sub x/N/sub y/) via the ND/sub 3/ annealing of Ta/sub 2/O/sub 5/, for use in gate dielectric applications. Compared with tantalum oxide (Ta/sub 2/O/sub 5/), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We were able to confirm nitrogen incorporation in the tantalum oxynitride (TaO/sub x/N/sub y/) by Auger electron spectroscopy. Compared with NH/sub 3/ nitridation, tantalum oxynitride prepared by nitridation in ND/sub 3/ shows less charge trapping and larger charge-to-breakdown characteristics.

30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE resistance

A novel ultrathin body SOI MOSFET with a recessed source-drain (S/D) structure is proposed to reduce the S/D extension (SDE) resistance and the feasibility on the proposed device is checked. A recessed buried oxide under the SDE regions is completely filled with the heavily doped polysilicon, which can lead to a low SDE resistance. A recessed S/D SOI MOSFET with 30 nm gate length and 5 nm thick undoped channel, was successfully fabricated and showed the good SCE immunities; little punch-through, the drain-induced barrier lowering of 140 mV/V, and the subthreshold slope of 79 mV/dec.

Plasma doping technology for fabrication of nanoscale metal-oxide-semiconductor devices

We developed a plasma doping (PLAD) technique which is appropriate for the nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) fabrications. Silicon-on-insulator (SOI) n-MOSFETs with a 50-nm-length metal gate and a 100-nm-channel width were successfully fabricated. The source and drain extensions (SDE) of SOI n-MOSFETs were formed using a plasma doping technique. The advantage of this process is the exclusion of additional activation annealing after introduction of impurity in SDE, which resulted in a laterally abrupt source/drain (S/D) junction profile. We can obtain a low sheet resistance by the PLAD technique and low damaged shallow junctions. A trigate structure SOI n-MOSFET with a gate length of 50nm fabricated by high-temperature plasma doping revealed suppressed short-channel effects.

Electrical characteristics of a TaOxNy/ZrSixOy stack gate dielectric for metal–oxide–semiconductor device applications

In this letter, we describe a process for the preparation of high-quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional chemical oxide and nitride as interfacial layers, TaOxNy metal–oxide–semiconductor capacitors using ZrSixOy as an interfacial layer exhibit lower leakage current levels at the same oxide thickness and a lower interface state density. We were able to confirm the TaOxNy/ZrSixOy stack structure by Auger electron spectroscopy and transmission electron microscopy analyses. Zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

Formation of a self-aligned hard mask using hydrogen silsesquioxane

A process to form a self-aligned hard mask using hydrogen silsesquioxane (HSQ) was investigated. Application of the flowing property of HSQ to form a hard mask is the main concept underlying the proposed process. When HSQ is coated on a wafer, most of it remains beside the pattern. Using the thick remaining HSQ beside the pattern as a hard mask, we could reduce the height of the pattern exclusively without etching beside the pattern region by the dry etching process. The proposed mask process was successfully applied to fabricate a poly-Si elevated source drain ultrathin body silicon on insulator metal-oxide-semiconductor field effect transistor.