Hyung-Rae Lee

Reflectivity-induced Variation in Implant Layer Lithography

Scaling of designs to the 45nm and future nodes presents challenges for block level lithography. Shrinking distances between devices drive aggressive resist placement tolerances, challenging the ability to control critical dimension (CD). In particular, the potential variation in shallow trench isolation oxide may result in variation of resist profile and CD, thereby affecting edge placement accuracy. Potential sources of this include wafer-to-wafer or within-wafer STI trench depth variations, and STI CMP variations that may be induced by active area pattern density fluctuations. Some other potential sources of CD fluctuation include oxide sidewall variation, and implant level overlay or CD errors modulating the proximity to the oxide sidewall. Depending on the actual variation of isolation oxide and the exposure latitude of the resist, the CD variations simply from oxide variation may consume a large portion of the CD budget. Several examples are given of variations in resist profile and CD arising from these substrate effects. The CD uniformity of a test structure was shown to decrease dramatically with the addition of a BARC to the resist stack, most likely due to the suppression of substrate reflectivity variations. Simulations performed using Panoramic Technologies software demonstrated the potential sensitivity of the factors outlined above on CD and profile errors. A comparison of simulated vs. experimental results is made for a case of intentional overlay error, showing the failure mode of the resist profile as the mask edge passes from STI to the active area. The simulations using a full physical model provided with the simulation software predict a resist foot forming over the active area, which was confirmed experimentally.

Message to the undecided - Using DUV dBARC for 32 nm node implants

In recent years, implant (block) level lithography has been transformed from being widely viewed as non-critical into one of the forefronts of material development. Ever-increasing list of substrates, coatings and films in the underlying stack clearly dictates the need for new materials and increased attention to this challenging area. Control of the substrate reflectivity and critical dimension (CD) on topography has become one of the key challenges for block level lithography and is required in order to meet their aggressive requirements for developing 32nm technology and beyond. The simulation results of wet-developable bottom anti-reflective coating (dBARC) show better reflectivity control on topography than the conventional top anti-reflective materials (TARCs), and make a convincing statement as to viability of dBARC as a working solution for block level lithography.1 Wet-developable BARC by definition offers substrate reflectivity and resist adhesion control, however there is a need to better understand the fundamental limitations of the dBARC process in comparison to the TARC process. In addition, some specific niche dBARC applications as facilitating adhesion to challenging substrates, such as capping layers in the high-k metal gate (HK/MG) stack, can also be envisioned as most imminent dBARC applications.2 However, most of the engineering community is still indecisive to use dBARC in production, bound by uncertainties of the robustness and lack of experience using dBARC in production. This work is designed to inspire more confidence in the potential use of this technology. Its objective is to describe testing of one of dBARC materials, which is not a photosensitive type, and its implementation on 32nm logic devices. The comparison between dBARC and TARC processes evaluates impacts of dBARC use in the lithographic process, with special attention to OPC behavior and reflectivity for controlling CD uniformity. This work also shows advantages and future challenges of dBARC process with several 248nm and 193nm resists on integrated wafers, which have shallow trench isolation (STI) and poly gate pattern topography.

Comprehensive analysis of sources of total CD variation in ArF resist perspective

ArF lithography has been successfully implemented for the development of sub-90nm DRAM devices. Line width control for the ArF lithography is becoming increasingly challenging as design rules shrink. Many works have been performed on the mask, exposure tools, and tracks to obtain better critical dimension (CD) uniformity, however in-field uniformity, in-wafer uniformity, and wafer-to-wafer uniformity from resist itself was not considered thoroughly. In this experiment, resist parameters that contributes to line width variation were considered in resist perspective. For the in-field uniformity, mask CD uniformity is very important. However, the mask error enhancement factor (MEEF) was different ranging from 3.27 to 5.12 depending on the resists in the k1 0.35 processes even though the screened resists met all the required resolution, depth of focus (DOF), exposure latitude (EL), line edge roughness (LER), and profile. For the resists having good MEEF, the in-filed uniformities of the critical layers were highly improved. The PEB sensitivities of the screened resists were evaluated again in terms of post exposure bake (PEB) sensitivity, which were quite higher than those of KrF resists. They ranged from 4.0 to 11.3 nm/°C. In-wafer uniformity was evaluated and compared using the resists having different PEB sensitivity. The resist with better PEB sensitivity showed better result in in-wafer uniformity. Finally, the wafer-to-wafer uniformities of the resists were evaluated. There was different delay after exposure depending on the sequence of the loaded wafers because it was not easy to control the delay time at the interface of a scanner and a track. The CD increased depending on the sequence, and it coincided well with the delay time of the wafers after exposure. The wafer-to-wafer CD variations were improved using the resists having strong resistance to the delay.

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

C-quad polarized illumination for back end thin wire: moving beyond annular illumination regime

The objective of this work is to describe the advances in the use of C-Quad polarized illumination for densest pitches in back end of line thin wire in 32m technology and outlook for 28 nm technology with NA of 1.35 on a 193nm wavelength scanner. Through simulation and experiments, we found that moving from Annular to C-Quad illumination provides improvement in intensity and contrast. We studied the patterning performance of C-Quad illumination for 1D dense, semi dense, isolated features with and without polarization. Polarization shows great improvement in contrast and line edge roughness for dense pattern. Patterning performance of isolated and semi-isolated features was the same with and without polarization.

Application of bi-layer resist on 70 nm node memory devices

Bi-Layer Resist (BLR) process has been developed as an alternative method to overcome the limit of Single-Layer Resist lithography. Compared to other methods such as Single-Layer Resist (SLR) and Multi-Layer Resist (MLR), BLR has distinct advantages in cost down effect and quick Turn-Around-Time (TAT) due to the reduced number of process steps. In addition, it yields acceptional improvement in the Line-Width Roughness (LWR) on smaller CD. We have obtained feasible results of dense line and space patterning on various devices, which has 70 nm design rule. In this paper, a scanner of NA 0.85 is used and then appropriate condition of dry etch without any grass defect is developed. We are certain that BLR process is a strong candidate approach for the extension technology of ArF lithography and has potentially applicable in various devices.

Evaluation of puddle time effect and optimization of development process in 193-nm lithography

The development process is very important in determining the resolution of the lithography process. As the shrinkage of design rule approaches to sub-100nm, understanding of dissolution mechanism and optimization of development process are needed to control the critical dimension (CD) and to obtain the best lithography performance. It was expected that more diluted developer solution could be used and appropriate for the 193nm lithography. But it has a serious issue in terms of changing and handling the concentration of developer solution in a factory, so application of diluted developer solution to lithography process is expected to be difficult. With this problem in mind, we focus on shortening process time during development stage instead of application of diluted solution, which has a demerit in mass production. Process margins of short time process were evaluated and compared with those of normal development process in 193nm lithography. This short time process was proved to be applicable to 193nm lithography and confirmed in view of line edge roughness (LER), in-wafer CD uniformity, mask error enhancement factor (MEEF), a bias between isolated and dense pattern (ID bias) and so on. This also could make it possible to improve the track throughput, which amount of increment may be 24 wafers per hour in 4 development modules.