Han-Ku Cho

Experimental investigation of the impact of LWR on sub-100-nm device performance

Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.

Effects of various plasma pretreatments on 193nm photoresist and linewidth roughness after etching

Among the pretreatment methods which are performed just after the lithographic process to minimize the roughness increase of 193nm photoresist during the subsequent etching processes, an in situ plasma pretreatment is the most cost effective. A HBr plasma pretreatment has proven quite effective and a few papers have described the mechanism. In an effort to understand further, the authors evaluated four plasma pretreatments using HBr, Ar, H2, or Cl2 gases and compared their results. Fourier transform infrared (FTIR) spectroscopy was performed for the investigation of the chemical changes effected by the plasma pretreatments. Cross-section scanning electron microscope (SEM) images were used to measure the photoresist film thickness, while top-down SEM images and an off-line program were used to determine linewidth roughness (LWR) changes for 70 and 80nm line features. They found two different types of roughness. The first type is a low-frequency roughness, which repeats about every 400nm and increases the L...

Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100 nm device performance

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

Double-Patterning Technique Using Plasma Treatment of Photoresist

The double-patterning process was investigated for line-and-space (L/S) patterns of 65 nm half pitch [k1=0.286, 0.85-numerical aperture (NA) ArF dry system] by plasma treatment of photoresist (PR). The sequence of this patterning is exposure–plasma treatment–exposure–etching. Si thin-film passivation and HBr plasma treatment (HPT) were applied, and Si thin-film passivation is preferred to HPT in terms of intermixing prevention and etch selectivity. For planarization of the topographic surface, a thick bottom PR was coated on the pattern after the first exposure. Si thin-film passivation and the thick bottom PR enabled the second exposure to be separated from the first exposure. After the etching process was completed down to the nitride hardmask material, the L/S patterns of 65 nm half pitch were achieved at the full-chip level by virtue of the Si thin-film passivation and thick bottom PR. In the meantime, considering the layout characteristic and process flexibility, layout decomposition and the optical proximity correction (OPC) process were performed. Even though the 65 nm half pitch is defined to be such that k1=0.286, it is believed that this double patterning scheme we suggested can be applied at the minimum pitch over the theoretical limit below 0.25. Consequently, it is expected that the double-patterning technique (DPT) process will have an important role in the extremely low k1 lithography beyond the 32 nm node.

New types of dose distributions for vertical sidewall minimizing total dose in 3-D electron-beam proximity effect correction of nanoscale features

The spatial dose distribution across a feature, derived by a conventional 2-D proximity effect correction scheme, is a “V-shape,” i.e., higher dose closer to edges. With such a dose distribution, it is extremely difficult to realize a vertical sidewall in the resist profile for nanoscale features while reducing the critical dimension (CD) error. In this paper, it is shown that, in order to achieve a vertical sidewall of nanoscale feature with the minimum total dose, a dose distribution of a shape other than the V-shape must be used. This is due to the fact that the lateral development of resist becomes comparable to the vertical development for nanoscale features and the exposure varies along the depth dimension with high and low contrasts at the top and bottom layers of resist, respectively. Based on these characteristics, new types of dose distributions, i.e., “M-shape” and “A-shape,” have been derived to achieve a target resist profile of a vertical sidewall while minimizing the total dose. The simulat...

Three-dimensional proximity effect correction for large-scale uniform patterns

One of the major limiting factors in electron beam (e-beam) lithography is the geometric distortion of written features due to electron scattering, which is known as the proximity effect. A conventional approach to the proximity effect correction (PEC) is, through 2D simulation, to determine the dose distribution and/or shape modification for each feature in a circuit pattern such that the written pattern is as close to the target pattern as possible. Earlier, it was shown that the 3D PEC, which considers the variation of exposure along the resist-depth dimension, would be necessary for the feature size well below 100 nm. Also, a feature-by-feature correction procedure is too time-consuming to be practical, especially for the 3D PEC of large-scale patterns. In this paper, a new method for the 3D PEC is proposed, which adopts 3D resist profile (instead of 2D exposure distribution) in optimization, but avoids the intensive computation by employing a critical-location-based correction procedure. The proposed...

CD uniformity improvement for EUV resists process: EUV resolution enhancement layer

Extreme ultra violet (EUV) resists have been developed to be able to print sub-30nm L/S features with EUV alpha DEMO tool (ADT) having 0.25NA. However, a lithographic performance of EUV resist is not comparable to that of DUV resist. At same process constant (k1), the imaging capability of EUV resist is poor than that of DUV resists. The most critical issues are line width roughness (LWR) and critical dimension (CD) variation across a field. Although there are many studies to improve the LWR of EUV resist, the issue on CD variation across a field is not much explored, because the problem can be detected at full field exposure. In this paper, sources of the CD variation across a field are mainly investigated, and solutions to improve the CD uniformity are explored. Out of band (OOB) radiation and its reflectivity at REticle MAsking (REMA) unit of scanner or absorber of mask is regarded as one of the sources which aggravates imaging quality of EUV resist. In addition, the optical density of black border at EUV wavelength is also known to have an impact on this CD variation. Although the exact spectrum of OOB radiation is not open, LASER produced plasma (LPP) type source and discharge produced plasma (DPP) type source are believed to have the OOB radiation. Therefore, to improve pattern fidelity and LWR of EUV resist, the mitigation of OOB radiation impact is required. It is found that the resist sensitivity to DUV compared to EUV is important, and this property affects on CD uniformity. Furthermore, new material which can mitigate the OOB radiation impact is developed. This material is applied as an additional layer on conventional EUV resist film, and shows no intermixing. Process window is not changed by applying this layer. The filtering ability of OOB radiation is explored. LWR and pattern fidelity are much improved by applying this material to EUV process.

Absorber stack optimization in EUVL masks: lithographic performances in alpha demo tool and other issues

Thinner absorber structure in EUVL mask is supposed to be applied in 2x HP node since it shows several advantages including H-V bias reduction. Here, lithographic performances of EUVL masks as a function of absorber stack height are investigated using ADT exposure experiments. Wafer SEM images show that minimum resolution is almost identical at ~27.5 nm with absorber thickness ranging from 45 to 70 nm. Simulations also exhibit that NILS and contrast become maximized and saturated in those ranges. However, thinner absorber structure using 50-nm-thick absorber shows much lower H-V bias than conventional structure using 70-nm-thick absorber. MEEF, EL, DOF, and LWR are also slightly improved with thinner absorber. One of the noticeable issues in thin absorber is low OD which results in pattern damages and CD reduction at shot edges due to light leakage from the neighboring exposures. To overcome these issues, appropriate light shielding process during mask fabrication as well as minimizing OoB radiation in EUVL scanner are required. Another item to prepare for 2x HP node is to increase defect detection sensitivity with 19x nm inspection tools. Thus, absorber stacks with new ARC layer optimized for 19x nm inspection should be developed and applied in EUVL mask blanks.

Effects of mask absorber structures on the extreme ultraviolet lithography

In this paper, the authors present the results of an investigation of the dependence of mask absorber thickness on the extreme ultraviolet lithography (EUVL) and suggest a new mask structure to minimize shadowing effects. For this purpose, several patterned masks with various TaN absorber thicknesses are fabricated using in-house Ru-capped EUVL mask blanks. According to the simulation using practical refractive indices, which are obtained at EUV wavelengths, the absorber thickness can be reduced to that of out-of-phase (ΔΦ=180°) ranges without loss of image contrast and normalized image log slope. Thickness to meet out-of-phase in real mask can be obtained by comparing field spectrum intensity ratio using the EUV coherent scattering microscopy (CSM). 52.4nm in thickness is close to ΔΦ=180° for TaN absorber since it shows the highest 1st/0th order intensity ratio as well as the best resolution in the microfield exposure tool (MET) test. When we apply 40-nm-thick TaN instead of 80-nm-thick TaN, the amounts of H-V bias reduction in wafer scale correspond to 80% (2.46–0.48nm) by CSM and 70% (2.23–0.65nm) by MET test results. Considering the fact that H-V bias in the MET is similar with that of simulation using the resist model, the degree of H-V bias in the alpha demo tool (ADT) is supposed to be much higher than that of MET due to its higher incident angle (θ=6°). Our final goal is to develop a thin absorber EUVL mask which has a low H-V bias, high EUV printability and DUV contrast, and sufficient optical density at the border. To achieve this, blind layer treatment and integration with anti-reflective coating layer are in progress.In this paper, the authors present the results of an investigation of the dependence of mask absorber thickness on the extreme ultraviolet lithography (EUVL) and suggest a new mask structure to minimize shadowing effects. For this purpose, several patterned masks with various TaN absorber thicknesses are fabricated using in-house Ru-capped EUVL mask blanks. According to the simulation using practical refractive indices, which are obtained at EUV wavelengths, the absorber thickness can be reduced to that of out-of-phase (ΔΦ=180°) ranges without loss of image contrast and normalized image log slope. Thickness to meet out-of-phase in real mask can be obtained by comparing field spectrum intensity ratio using the EUV coherent scattering microscopy (CSM). 52.4nm in thickness is close to ΔΦ=180° for TaN absorber since it shows the highest 1st/0th order intensity ratio as well as the best resolution in the microfield exposure tool (MET) test. When we apply 40-nm-thick TaN instead of 80-nm-thick TaN, the amounts ...

Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography

The patterning of sub-80 nm contact holes and trenches by ArF lithography is very challenging. To solve this problem, several technologies have been proposed, including thermal flow, resolution enhancement of lithography assisted by chemical shrink (RELACS), and shrink assist film for enhanced resolution (SAFIER). In this paper, we compare these processes in order to determine the advantages and disadvantages, and to gain an understanding on their mechanism on the basis of the performances of each process. Thermal flow shows a strong advantage in terms of simplicity, but it shows several disadvantages in terms of layout dependence, mask error enhancement factor (MEEF), and process window. RELACS is proven to be the most reliable, since there is a small shrink amount dependence on layout and temperature, but the limitation of shrink amount is an obstacle. Finally, SAFIER shows strong advantages in low MEEF, wide process window, and enhanced uniformity, with a weakness of the deformation in asymmetric pattern. It is considered that such performances are strongly related to the mechanism of each process, and therefore, the process should be used according to its own performances and mechanism. On the basis of the properties and relationship with the mechanism, the appropriate applications are recommended for each process.