Sang-Gyun Woo

Experimental investigation of the impact of LWR on sub-100-nm device performance

Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.

Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100 nm device performance

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

Trade-off between Inverse Lithography Mask Complexity and Lithographic Performance

Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.

Analysis of process margin in EUV mask repair with nano-machining

Reduced design rules demand higher sensitivity of inspection, and thus small defects which did not affect printability before require repair now. The trend is expected to be similar in extreme ultraviolet lithography (EUVL) which is a promising candidate for sub 32 nm node devices due to high printing resolution. The appropriate repair tool for the small defects is a nanomachining system. An area which remains to be studied is the nano-machining system performance regarding repair of the defects without causing multilayer damage. Currently, nanomachining Z-depth controllability is 3 nm while the Ru-capping layer is 2.5 nm thick in a Buffer-less Ru-capped EUV mask. For this report, new repair processes are studied in conjunction with the machining behavior of the different EUVL mask layers. Repair applications to achieve the Edge Placement(EP) and Z-depth controllability for an optimal printability process window are discussed. Repair feasibility was determined using a EUV micro exposure tool (MET) and Actinic Imaging Tool (AIT) to evaluate repairs the 30 nm and 40 nm nodes. Finally, we will report the process margin of the repair through Slitho-EUVTM simulation by controlling side wall angle, Z-depth, and EP (Edge Placement) on the base of 3-dimensional experimental result.

Attenuated phase-shifting masks of chromium aluminum oxide

Chromium aluminum oxide was chosen as a new candidate for use as an attenuated phase-shifting mask (Att-PSM) material. The compositions of films were correlated with optical properties. With the measured and the fitted data, we simulated the transmittance and the phase shift using the matrix method. Consequently, we acquired optimum parameters for Att-PSMs, such as Al/Cr = 1.9-2.5 and d = 120 nm at a 193-nm wavelength, Al/Cr = 1.0-1.7 and d = 128 nm at a 248-nm wavelength, and Al/Cr = 0-0.1 and d = 170 nm at a 365-nm wavelength. This simulation was verified by transmittance measurement.

Simulation and fabrication of attenuated phase-shifting masks: CrF x

To acquire the required resolution for 248- and 193-nm lithography, a study of attenuated phase-shifting mask (Att-PSM) technology is in progress. We performed a simulation study using a matrix method to calculate relative transmittance and the amount of phase shift of light through the PSM. However, we found that the average film composition changed with deposition time. Accordingly, optical constants were found to be a strong function of film thickness. Therefore we rearranged the relationship between deposition parameters (e.g., deposition time or gas flow rate ratio) and optical constants (e.g., refractive index and extinction coefficient) to extract the empirical formula for the optical constants with respect to film composition. To verify our simulation study, we fabricated a phase shifter based on our simulation result, which was found to have a transmittance of 8.3% and a phase shift of 179.5 degrees . Consequently, we obtained a reliable optimum condition for the deep-ultraviolet Att-PSM.

Macro analysis of line edge and line width roughness

Line edge and line width roughness (LER/LWR) is commonly estimated by standard deviation sigma. Since the standard deviation is a function of sample line length L, the behavior of sigma(L) curve is characterized by the correlation length and roughness exponent. In this paper, an efficient and practical macro LER/LWR analysis is implemented by characterizing an arbitrary array of similar features within a single CD-SEM image. A large amount of statistical data is saved from a single scan image. As a result, it reports full LER/LWR information including correlation length, roughness exponent, sigma at infinite line length, and power spectrum. Off-line, in-house software is developed for automated investigation, and it is successfully evaluated against various patterns. Starting with the detailed description of the algorithm, experimental results are discussed.

Flare in Microlithographic Exposure Tools

To achieve the high level in photolithographic technology that is needed for current microelectronic devices, it is strongly required to consider emerging key parameters that were not critical drawbacks in previous photolithographic techniques. Flare existing in optical elements is one example of such emerging key parameters. In this paper, undesirable linewidth variation due to flare and a measurement method of flare are described. Various phenomena related to linewidth variation due to flare are experimentally observed and theoretically analyzed. Finally, the photomask linewidth correction is introduced to compensate this undesirable linewidth variation due to flare.

Mask writing time explosion and its effect on CD control in e-beam lithography

As semiconductor features shrink in size and pitch, the extreme control of CD uniformity and MTT is needed for mask fabrication with e-beam lithography. And because of huge shot density of data, the writing time of e-beam lithography for mask fabrication will be increased rapidly in future design node. The beam drift caused by charging of optic system and current density drift can affect the beam size, position and exposure dose stability. From the empirical data, those are the function of writing time. Although e-beam lithography tool has the correction function which can be applied during writing, there are remained errors after correction which result in CD uniformity error. According to the writing time increasing, the residual error of correction will be more important and give the limit of CD uniformity and MTT. In this study, we study the beam size and exposure dose error as a function of time. Those are mainly caused by charging and current density drift. And we present the predicted writing time of e-beam lithography below 32nm node and estimate its effect on CD control error. From the relation between writing time and CD control error, we achieve the limit of CD uniformity with e-beam mask writer. And we suggest the method to achieve required CD uniformity at 22nm node and beyond.

Substrate effects on the characteristics of Haze defect formation on the photomask surface under exposure condition

We have explored substrate effects upon the characteristics of haze creation on the mask surface by performing surface analysis for each of Cr, MoSiON, and Qz substrates of the mask before and after laser exposure. We found out chemical ions such as sulfur and ammonium ions should have different mobility behavior towards haze defect creation depending on each substrate during laser exposure. This fact can partially clarify the reason why haze occurrence on the mask in real mass production mainly comes up with Qz substrate surface even though it has the lowest level of chemical residue on it. We also realized that sulfur ions are penetrating into a sub layer of Qz substrate and even deeper during laser exposure, which signifies that we may have to remove a thin surface layer from Qz substrate to further improve haze issue from the current standpoint.