Hyung Soo Uh

Process design and emission properties of gated n+ polycrystalline silicon field emitter arrays for flat-panel display applications

The gated n+ polycrystalline silicon (poly-Si) field emitter arrays (FEAs) have been designed and successfully fabricated on an oxidized silicon wafer for large display applications. The proposed structure of the FEAs eliminates the difficulty of having the cathode electrode (n+ diffusion layer)-to-cathode electrode isolation, which is common to crystalline silicon (c-Si) field emitter arrays. Compared with c-Si field emitters, poly-Si emitters showed poor uniformity in device structure such as emitter shape and gate hole, which was thought to be due to the variation of the grain size of poly-Si and the oxide thickness associated with grain boundaries of poly-Si in the sharpening oxidation step. The anode current of 0.1 μA/tip was measured at the gate bias of 82 V from poly-Si emitters with gate hole diameter of 1.2 μm under the vacuum pressure of 3×10−9 Torr. The same anode current was obtained at 80 V from c-Si emitters with the gate hole diameter of 1.6 μm. The gate leakage current for both the c-Si FE...

The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors

The electron potential of a photodiode in a CMOS image sensor should be designed precisely since the charge capacity of the photodiode decreases as the pixel area shrinks. The pinch-off voltage of a photodiode, which also affects the electron capacity, is dependant on the doping profile of the pn junction as well as the size of the photodiode. The pinch-off voltage is lower in a smaller photodiode. A simple method that uses the lateral depletion of a photodiode for an estimate of the pinch-off voltage in small photodiodes is proposed, and is compared to the measured experimental data. Two constants are used to account for the doping profile and photodiode size. The measurement data shows the error of the estimation of the pinch-off voltage to be <0.05V.

A novel fabrication process of a silicon field emitter array with thermal oxide as a gate insulator

We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si/sub 3/N/sub 4/ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 /spl mu/A (1 /spl mu/A) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels. >

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

Surface application of molybdenum silicide onto gated poly-Si emitters for enhanced field emission performance

This article investigates the merits of molybdenum (Mo) silicide formation on gated polycrystalline silicon (poly-Si) field emitters. Metal silicides are promising materials for field emission cathode due to their high electrical and thermal conductivity and high-temperature stability. In our experiment, Mo silicide was produced by direct metallurgical reaction, that is, deposition of Mo and subsequent rapid thermal annealing. The surface morphologies and field emission properties of Mo-silicided poly-Si (Mo-polycide) emitters have been examined and compared with those of pure poly-Si emitters. Field emission from these Mo-polycide emitters exhibited significant enhancement compared with pure poly-Si emitters in both total emission current and stability. The reason for this improved electron emission efficiency and stability could be explained by the smaller work function and better surface inertness of Mo-polycide emitters than those of poly-Si emitters.

Characteristics and circuit model of a field emission triode

A circuit model for a field emission triode has been proposed. The model parameters have been extracted from the fabricated silicon tip array and verified by comparing with the results simulated by circuit simulator (SPICE). The cut-off frequency can be calculated from the parametric capacitance and the transconductance values extracted from measurements. For the field emission triode, the capacitance of 3.45 fF/tip and the transconductance of 0.94 nS/tip have been measured under the emission current of 4.1 nA/tip. From these values, the cut-off frequency is predicted to be 43 kHz but the measured one came out to be 6kHz. because of the parasitic capacitance components.

Improvement of electron emission efficiency and stability by surface application of molybdenum silicide onto gated poly-Si field emitters

As an approach to improve electron field emission and its stability, molybdenum (Mo) silicide formation on n/sup +/ polycrystalline silicon (poly-Si) emitters has been investigated. Mo silicide was produced by direct metallurgical reaction, namely, deposition of Mo and subsequent rapid thermal annealing. The surface morphologies and emission properties of Mo-silicided poly-Si (Mo-polycide) emitters have been examined and compared with those of poly-Si emitters. While anode current of 0.1 /spl mu/A per tip could be obtained at the gate voltage of 82 V from poly-Si emitters, the same current level was measured at 72 V from Mo-polycide emitters. In addition, the application of Mo silicide onto poly-Si emitters reduced the emission current fluctuation considerably. These results show that the polycide emitters can have potential applications in vacuum microelectronics to obtain superior electron emission efficiency and stability.

New fabrication method of silicon field emitter arrays using thermal oxidation

The fabrication and emission characteristics of a silicon field emitter array using pure thermal oxide as a gate insulator are described. Since the thermally grown oxide film has a better stoichiometry and is a better insulator than the evaporated oxide, the fabrication process could be stabilized and the tip‐to‐tip uniformity improved. In addition, the aspect ratio can be controlled easily by this process free from the shadowing effect that appears in the evaporation process. Fabricated samples have been measured electrically in the vacuum of 1×10−8 Torr. The anode current of 290 nA (37 nA) for a single tip was observed at the gate voltage of 130 V (100 V), and the gate current was less than 1% of the emission current. The emission patterns of a 625‐tip array showed a very uniform phosphor luminescence due to the averaging effect resulting from the multiple silicon tips.

Fabrication and characterization of gated n/sup +/ polycrystalline silicon field emitter arrays

Field emission characteristics from n/sup +/ polycrystalline silicon (poly-Si) field emitters fabricated on an insulating layer are presented and compared with those from single crystal silicon field emitters. SEM micrographs of fabricated poly-Si emitters showed poor uniformity in structure due to the oxide thickness deviation associated with grain boundaries of poly-Si in sharpening oxidation step. The anode current of 0.1 /spl mu/A/tip was measured at the gate bias of 82 V from 625 poly-Si tips with gate hole diameter of 1.2 /spl mu/m and 80 V from 625 single crystal Si tips with diameter of 1.6 /spl mu/m, respectively.

Surface morphology and I-V characteristics of single-crystal, polycrystalline, and amorphous silicon FEA's

This letter reports the surface morphology and current-voltage (I-V) characteristics of single-crystal silicon (c-Si), polycrystalline silicon (poly-Si), and amorphous silicon (a-Si) field emitter arrays (FEAs). As-deposited a-Si film has a smoother surface than poly-Si film. The surface morphology of the a-Si remains smooth even after phosphorus doping and oxidation at 950/spl deg/C to be improved in emission characteristics, i.e., smaller anode current deviation among arrays smaller gate current, and higher failure voltage than those of poly-Si FEAs. Such improved characteristics can be explained by the smooth surface morphology which is kept during doping and oxidation. The surface roughness and emission characteristics of a-Si FEAs are comparable to those of c-Si FEAs.