Myounggon Kang

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

A simple parameter extraction method of spiral on-chip inductors

Accurate measurement and parameter extraction for spiral inductors are very important in monolithic microwave integrated circuit (MMIC) design. In this paper, we have proposed an easy and simple model parameter extraction method of wide-band on-chip inductor. The simple extraction methodology is applied to extract parameters from the measured S-parameters of spiral inductors fabricated with 0.18-/spl mu/m CMOS technology. Model prediction shows excellent agreement with the measured data over a wide frequency region. Also, the model can be easily integrated in SPICE-compatible simulators because all the elements are frequency independent. This method will provide practical and useful circuit parameters for MMIC design.

Activation Energies

The conventional temperature-accelerated lifetime test method of NAND Flash memory does not follow the Arrhenius model, as various failure mechanisms occur concurrently. We completely separated three main failure mechanisms and extracted each activation energy (Ea) value in three generations (A, B, C) of advanced NAND Flash memory. We compared and analyzed each value of Ea of the three main mechanisms with different device generations and cycling times. The results confirmed that each failure mechanism follows the Arrhenius law. The extracted Ea values of the detrapping mechanism were almost the same (Ea ~ 1.0 eV) regardless of the generation or the cycling times because they are determined by the rate of change of the detrapping probability of each trapped electron according to the baking temperature, not the surface area or trap density. However, the Ea value of the trap-assisted tunneling (TAT) mechanism is dependent on the generation and cycling times. Both the dominant trap energy levels and the average distance between the traps in the oxide layer have a strong impact on the Eavalue of the TAT mechanism. The interface trap recovery mechanism has very small time-constant (τ), and its activation energy is very small (Ea ~ 0.2 eV).

(E_{a})

In this letter, we point out the methodological problem of the conventional temperature-accelerated life-test method of nand Flash memory. We confirm that the generally assumed Arrhenius law is inconsistent with extrapolation of data-retention time-to-failure of nand Flash memory since several failure mechanisms come up together. For the first time, we completely separated three main failure mechanisms and extracted each activation energy (Ea) in 21-nm nand Flash memory. From the results, we assured that each failure mechanism follows the Arrhenius law. In order to estimate the lifetime of nand Flash memory accurately, each failure mechanism should be considered.

of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling

We propose an accurate compact model of NAND Flash memory, which is fully compatible with a BSIM-4 model. In sub-30-nm NAND Flash, adjacent cells directly affect the channel-edge potential of the selected cell. Due to such direct-channel interference, previous compact models cannot accurately simulate the characteristics of sub-30-nm NAND strings. In this letter, we describe the interference as the threshold voltage variation due to adjacent cells and change the threshold voltage equation of the BSIM-4 model. The equation is semitheoretically derived. Using the proposed model, we simulated several behaviors of 27-nm NAND Flash strings. The results show more than 90% accuracy compared with the silicon measurements.

Analysis of Failure Mechanisms and Extraction of Activation Energies

In this letter, we separated the corner and plane component of trap-assisted tunneling (TAT) mechanism and analyzed the retention characteristics in the worlds smallest NAND flash memory (1X-nm generation). We found that the Ea of the corner component in TAT mechanism is smaller than that of the plane component due to the higher crowding electric field and larger trap density. The extracted Ea of both the components at the highest programmed Vth level (i.e., PV3 state) is smaller than that at PV2 state since the larger number of the stored electrons in floating gate increases the electric field across the tunneling oxide layer. It reduces the energy barrier between the traps and Ea. The ratio of the corner part over the plane one is larger at highly cycled and in smaller devices. For better understanding of the abnormal retention characteristics, each failure mechanism should be accurately analyzed.

(E_{a})

In this brief, we have investigated the program disturb characteristics caused by drain-induced barrier lowering (DIBL) in a 32-nm nand Flash memory device. It was found that the VTH shift of the (N + 2)th erased state cell is larger than that of the (N + 1)th erased state cell if it is assumed that the channel of the Nth cell is cut off. It is revealed that the cut off is caused by a cell-to-cell coupling effect that is becoming more severe in the development of high-density Flash memory arrays.

in 21-nm nand Flash Cells

A simple and accurate method is presented for extraction of the effective gate resistance of RF MOSFETs. Both the gate electrode resistance and the channel resistance were extracted separately. The proposed physics-based gate resistance model can accurately predict not only the bias dependency but also the dependence on the number of fingers, channel lengths, and widths

An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in Sub-30-nm nand Flash Technologies

We extracted final ΔV_th, time constant, and activation energy (E_a) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of V_th cumulative probability distribution. As a result, we confirmed that at lower P level, the final ΔV_th of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final ΔV_th of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger E_a at high P level, whereas the E_a of detrapping mechanism decreases because of barrier lowering effect.

Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory

New schemes of read operation using boosted channel potential of adjacent bit-line (BL) strings are proposed for improving on-state current of a cell string in nand Flash memory. The channel resistance of pass cells in a cell string under read operation is decreased by the electric field due to the boosted channel potential of adjacent BL strings, which increases on-state current of the cell string. Proposed schemes give much smaller read disturbance compared with conventional ones because the boosted channel potential of unselected BL strings prevents soft programming in cells of the unselected BL strings. It was also shown that new read operation of #2 scheme leads to suppress the background pattern dependence by ~58%, as compared with the conventional read operation scheme.