Wouns Yang

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9 nm and thin equivalent oxide thickness (EOT) of 0.9 nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.

Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond

For the first time, we have successfully fabricated fully integrated advanced bulk FinFETs featuring partially insulating oxide layers under source/drain (S/D), named partially-insulated- FinFETs (PI-FinFETs), to control subchannel on the bottom part of the gate in bulk FinFETs and suppress punchthrough and junction leakage currents. We observed that the junction leakage is improved about 50%, drain-induced barrier lowering (DIBL) about 25%, and lifetime of hot carrier effect (HCE) about 1 order in comparison with normal bulk FinFETs. Furthermore, we propose a novel PI-FinFET structure with pad-polysilicon side contact (PSC) in bulk-Si to reduce gate induced drain leakage (GIDL) and increase Ion with improved SCE immunity. The simulation of novel structure shows that Ion, DIBL and GIDL is improved dramatically with the same login comparison with bulk FinFETs. This advanced structure is suitable for the miniaturization of GIDL of bulk FinFETs with improved Ion, Ioff and DIBL characteristics

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

Analysis on data retention time of nano-scale DRAM and its prediction by probing the tail cell leakage current

Characteristics of the data retention time (tRET) of nano-scale DRAM have been described. In addition, new approaches to enhance tRET and their properties have been analyzed. To optimize the process, we developed the tRET-modeling methodology, which has a good agreement with experimental data. The key feature of the methodology is an indirect probing of the tail leakage current by fitting the leakage model to reproduce the measured characteristics of the retention. The model shows the GIDL current is a major factor determining tRET of 80nm RCAT technology.

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM

A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

A new bulk fin field-effect transistor (bulk FinFET) with a recessed channel structure is proposed as a future dynamic random access memory (DRAM) cell transistor following the recess-channel-array transistor (RCAT). An enlarged effective channel length improves the relationship between off-state channel leakage (Ioff) and gate-induced drain leakage (GIDL) current, which correspond to the static and dynamic retention characteristics of a DRAM chip. The high current drivability of FinFET is maintained even with a recessed channel. A recessed-channel FinFET (RC-FinFET) shows excellent DC characteristics (subthreshold swing, drain-induced barrier lowering and body-bias effect) and longer retention time than a conventional local-damascene FinFET (LD-FinFET).

Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer

This paper presents a detailed analysis of the reliability characteristics of partially-insulated FinFETs (PI-FinFETs) where a new source/drain structure was adapted using a pad-polysilicon side contact (PSC). The PSC structure shows excellent improvements in device performances mainly due to the increment of the contact area by using lateral faces of FinFETs. The hot carrier degradation characteristics are also improved in comparison with a conventional source/drain structure having planar contact. This is due to an advantageous impact ionization position. By applying PSC structure to Pi-FinFETs, an optimized source/drain structure of PI-FinFETs can be obtained with its own advantages.

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT) to suppress body effect of conventional RCAT and improve current drivability in DRAM cell. The Pi-RCAT demonstrated superior characteristics in body effect, subthreshold slope (SW) and higher current drivability with comparable Ion-Ioff characteristics in comparison with conventional RCAT. Furthermore, in the partially-insulated-STI (Pi-STI) of core and peripheral structure formed simultaneously, well isolation characteristic is improved remarkably due to increase of effective isolation path. In this paper, Pi-RCAT is proved to be effective for the scalability and drivability of RCAT, and Pi-STI is suitable for the improvement of chip shrinkage efficiency.