Hyunwon Moon

A fully differential LC-VCO using a new varactor control structure

This paper presents a fully differential inductor-capacitor voltage-controlled oscillator (LC-VCO) with a new differentially-tuned varactor structure. The proposed LC-VCO has lower phase noise and better robustness to the injected common-mode noise than the differentially-tuned LC-VCO using the previous antiparallel structure. The LC-VCO implemented using 0.5-/spl mu/m SiGe BiCMOS technology is tunable from 4.251 to 4.428 GHz and the measured phase noise is -119 dBc/Hz at 1-MHz offset over the entire tuning range. Its core current is only 1.7 mA at 2.5-V supply voltage.

A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS

Many mobile devices with personal navigation and location based services (LBS) are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS receiver together with cellular phones creates new challenges because leakage signals from the transmitters in 2G/3G systems are harmful interferers, making it difficult for the receiver to detect a weak GPS signal from satellites. In general, an external interstage SAW filter is used for rejecting blocking signals after the LNA. Recently, there have been attempts to remove the inter-stage SAW filter to minimize the number of external components required[1–3]. So, a single pre-select filter is only required to prevent the out-of-band signals from blocking the receiver between the antenna and the IC. Although previous publications utilize tuned LC loads to tolerate a strong interferer signal, the frequency selectivity of the LC resonators will show a limited performance because the center frequency of an LC-tuned structure is very dependent on PVT variations. In this paper, a fully integrated GPS receiver with robust characteristics against the large interferer signals is presented.

A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.

A 85-mW Multistandard Multiband CMOS Mobile TV Tuner for DVB-H/T, T-DMB, and ISDB-T Applications with FM Reception

A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a 0.18-mm CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T- DMB, and ISDB-T with a digital demodulator.

An Area-Efficient 0.13-μm CMOS Multiband WCDMA/HSDPA Receiver

In this paper, a multiband wideband code-division multiple access/high-speed downlink packet access direct-conversion receiver to cover all six Third-Generation Partnership Project bands is implemented in a 0.13-μm CMOS process. To reduce the increase of chip size due to implementation of the multimode multiband RF transceiver integrated circuit, a new integrated inductor structure sharing an inner diameter, a proposed mixed-type dc offset correction circuit, and a stacked structure of metal-insulator-metal and MOS capacitors is proposed. These silicon area reducing techniques can decrease the chip size by up to 30%. The measured full-path receiver performance is a noise figure of >3 dB, third-order intermodulation intercept point of > -17 dBm, and second-order intermodulation intercept point of > +30 dBm for all six bands. Its current consumption, including a frequency synthesizer, is 45 mA at 2.8-V supply voltage.

A 0.13-µm CMOS multi-band WCDMA/HSDPA receiver adopting silicon area reducing techniques

A multi-band WCDMA/HSDPA direct-conversion receiver to cover all six 3GPP bands is implemented in a 0.13-µm CMOS process. The integrated inductor structure sharing an inner diameter and the mixed-type DC offset correction technique are useful to reduce the increase of silicon area generated by realizing the multi-band multi-mode RF transceiver. The measured full-path receiver performance is NF of ≪ 3dB, IIP3 of ≫ −17dBm, and IIP2 of ≫ +30dBm for all six bands. Its current consumption including frequency synthesizer is 45mA at 2.8 V supply.

Differentially tuned LC-VCO using modified anti-parallel structure

This paper presents a new differentially tuned LC-VCO using a modified anti-parallel. The proposed LC-VCO has lower phase noise and better robustness to the common-mode noise than the previous differentially tuned LC-VCO using the anti-parallel structure. The proposed LC-VCO is implemented using SiGe BiCMOS process. It is tunable from 4.25 to 4.43 GHz and the measured phase noise is -103 dBc/Hz at 100 kHz offset and -119 dBc/Hz at 1 MHz offset over the entire tuning range. Also, its CMRR characteristic is improved about 2dB. Its core current is 1.7 mA at 2.5V supply voltage.

A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 ㎛ CMOS

A low noise and low power RF front-end for 5.8 ㎓ DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 ㎓ LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ㎛ CMOS process and draws 7.3 ㎃ from a 1.2 V supply voltage. It shows a voltage gain of 40 ㏈ and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a 0.18-mm CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOS

A fully integrated low-IF GPS receiver with minimum external components is implemented in a 65nm CMOS process. It has an integrated LNA and an active complex bandpass filter with a switchable signal bandwidth of 2MHz or 6 MHz to achieve the SNR improvement. To reduce power consumption, the current reusing method and current mode interface technique using a capacitive cross-coupled common-gate structure are applied. The measured noise figure of whole receiver including an external inter-stage SAW filter is 2.2dB. Its current consumption is 15mA at 1.8V supply.