Dong-Jin Keum

VCO gain calibration technique for GSM/EDGE polar modulated transmitter

This paper describes a VCO gain calibration technique for the two-point modulation scheme using Delta-Sigma frequency synthesizer. The proposed technique enables PLL-based phase modulator to have wide bandwidth with good signal quality. A fully integrated GSM/EDGE polar modulated transmitter, implemented in a 0.13 mum CMOS process, is presented to show the feasibility of this calibration technique. After the calibration, it shows a margin of 8 dB to the spectrum mask at 400 kHz offset with EVM of 2%.

An Area-Efficient 0.13-μm CMOS Multiband WCDMA/HSDPA Receiver

In this paper, a multiband wideband code-division multiple access/high-speed downlink packet access direct-conversion receiver to cover all six Third-Generation Partnership Project bands is implemented in a 0.13-μm CMOS process. To reduce the increase of chip size due to implementation of the multimode multiband RF transceiver integrated circuit, a new integrated inductor structure sharing an inner diameter, a proposed mixed-type dc offset correction circuit, and a stacked structure of metal-insulator-metal and MOS capacitors is proposed. These silicon area reducing techniques can decrease the chip size by up to 30%. The measured full-path receiver performance is a noise figure of >3 dB, third-order intermodulation intercept point of > -17 dBm, and second-order intermodulation intercept point of > +30 dBm for all six bands. Its current consumption, including a frequency synthesizer, is 45 mA at 2.8-V supply voltage.

A 0.13-μm CMOS Σ-Δ frequency synthesizer with an area optimizing LPF, fast AFC time, and a wideband VCO for WCDMA/GSM/GPRS/EDGE applications

Use This paper presents a fully integrated fractional-N frequency synthesizer (FNFS) with an area optimizing low pass filter (LPF), fast adaptive frequency calibration (AFC) time, and a wideband on-chip LC voltage-controlled oscillator (VCO) for WCDMA/GSM/GPRS/EDGE transceivers. The FNFS employs a staked structure of MIM and MOS capacitors for LPF to economize the area. Fast AFC time is realized by using the prescaler output signal as a discriminating clock. A 3-bit 3rd order Sigma-Delta modulator serves as a fractional engine. Phase switching type prescaler is used to reduce the quantization noise of Sigma-Delta modulator. A fast switching CP is introduced. LC VCO utilizes bond-wire inductors with high Q-factor and a small area. Digitally controlled crystal oscillator (DCXO) provides a reference signal of high spectral purity. A prototype has been implemented in 0.13 mum CMOS technology. The measurements results show that the AFC time is less than 20-mus, in-band phase noise is -94 dBc/Hz, and out-band phase noise are -123 dBc/Hz at 400 KHz offset frequency and - 145 dBc/Hz at 3 MHz offset frequency when the carrier frequency is 900 MHz. Reference spur level is less than -75 dBc.

A 0.13-µm CMOS multi-band WCDMA/HSDPA receiver adopting silicon area reducing techniques

A multi-band WCDMA/HSDPA direct-conversion receiver to cover all six 3GPP bands is implemented in a 0.13-µm CMOS process. The integrated inductor structure sharing an inner diameter and the mixed-type DC offset correction technique are useful to reduce the increase of silicon area generated by realizing the multi-band multi-mode RF transceiver. The measured full-path receiver performance is NF of ≪ 3dB, IIP3 of ≫ −17dBm, and IIP2 of ≫ +30dBm for all six bands. Its current consumption including frequency synthesizer is 45mA at 2.8 V supply.

A Mixer With Third-Order Nonlinearity Cancellation Technique for CDMA Applications

A feedforward technique to improve the third-order nonlinearity of mixers in a direct conversion transceiver is presented. The third-order intermodulation (IM3) generated by the main transconductance (Gm ) stage of mixer with inductively degenerated emitter is cancelled by that generated by the sub-Gm stage with degeneration resistor. The circuit allows the mixer to be optimized independently, and has minimal impact on noise figure (NF), gain, area, and current consumption. The proposed technique reduced IM3 by approximately 16 dB with a current increase of approximately 7%. The mixer achieved an input-referred third-order intercept point of 5 dBm, a gain of 37 dB, and an NF of 9.8 dB drawing 7.9 mA from a 2.85-V supply. The transceiver including the calibration circuitry was implemented in a SiGe bipolar transistor with fT= 35GHz for U.S. cellular code division multiple access application

Highly linear variable gain amplifiers with programmable temperature compensation for CDMA wireless applications

Highly linear and low power variable gain amplifiers (VGAs) with digitally programmable temperature compensation has been developed using a 15 GHz 0.5 /spl mu/m BiCMOS process for CDMA mobile phones. Receive-VGA (RxVGA) shows 135-dB gain control range, 4.95 dB noise figure at a maximum gain, and -1.35 dBm IIP3 at a minimum gain with current consumption of 8 mA. Transmit-VGA (TxVGA) shows an output P/sub 1 dB/ of 4.7 dBm with current consumption varying from 6 mA to 24 mA according to its gain. The temperature compensation has been achieved within /spl plusmn/0.2 dB variation over the entire temperature and gain range. In addition, for easy application of the VGAs for mobile handsets, a simple method is presented for a programmable temperature compensation. A two-bit digital input is used to modify the temperature compensation characteristics by 1.5 dB/1110/spl deg/C per a step.

A single-chip CDMA-2000 zero-IF transceiver for band-class 4 with GPS support

A single-chip cdma-2000 zero-IF transceiver has been successfully developed for band-class 4 (Korean-PCS band) with an additional GPS signal receiving functionality. The receiver showed excellent noise and linearity performance (full- path NF=2dB, IIP3=-6dBm) with very low phase-noise VCO (- 132dBc/Hz@1.25MHz/fOSC=3.71G). The Tx-Rx isolation turned out to be good enough for the sensitivity and single-tone desensitization requirement of the CDMA-2000 system. The IC was implemented on a 0.35mum SiGe BiCMOS technology.