Byeong-Ha Park

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

Phase frequency detectors for fast frequency acquisition in zero-dead-zone CPPLLs for mobile communication systems

This paper introduces a new-type phase-frequency-detector (PFD) for charge pump phase-locked-loops (CPPLLs). As the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property. The experimental results of the proposed PFD show the reduced frequency acquisition time by about 30% compared with the conventional PFD in the case of 70MHz voltage-controlled-oscillator (VCO) frequency hopping for PCS mobile applications. The PFD is designed and simulated by SPECTRE and the prototype, together with a frequency synthesizer, has been fabricated in a 0.5/spl mu/m BiCMOS technology.

A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications

This paper describes a quantization noise reduction method in DeltaSigma fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.

A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS

Many mobile devices with personal navigation and location based services (LBS) are rapidly increasing in importance in our life. In particular, smart-phones with embedded GPS receivers are still growing their share and soon they will be the main products in the handset market. Co-existence of a GPS receiver together with cellular phones creates new challenges because leakage signals from the transmitters in 2G/3G systems are harmful interferers, making it difficult for the receiver to detect a weak GPS signal from satellites. In general, an external interstage SAW filter is used for rejecting blocking signals after the LNA. Recently, there have been attempts to remove the inter-stage SAW filter to minimize the number of external components required[1–3]. So, a single pre-select filter is only required to prevent the out-of-band signals from blocking the receiver between the antenna and the IC. Although previous publications utilize tuned LC loads to tolerate a strong interferer signal, the frequency selectivity of the LC resonators will show a limited performance because the center frequency of an LC-tuned structure is very dependent on PVT variations. In this paper, a fully integrated GPS receiver with robust characteristics against the large interferer signals is presented.

A nightmare for CDMA RF receiver: the cross modulation

This paper presents a quantitative analysis on the cross modulation between transmitter CDMA leakage signal and single tone jammer signal, and some design guidelines for overcoming it in receiver design. The analysis shows that duplexer isolation and LNA IIP3 are responsible for the cross modulation. It also shows that LNA IIP3 required for meeting J-STD-018 PCS specification is about 4-5 dBm with duplexer isolation of 50 dB.

A

This paper describes a quantization noise reduction method in DeltaSigma fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. Combined with the hybrid FIR filtering, single-loop topology makes 4th-order and 5th-order DeltaSigma modulators possible for the type-2 4th-order PLL. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.

\Delta\Sigma

Envelope tracking (ET) prolongs the battery life by modulating the supply of a power amplifier (PA) according to the signal envelope. With this emerging technology, the PA efficiency is greatly improved, whereas the supply modulator (SM) itself needs to provide efficient and accurate envelope tracking for the overall performance of the SM-PA combined system (PA module). The ET technique, meanwhile, has seen limited use in high-power transmission due to the reduced SM efficiency for low output power originating from the linear stage in hybrid structures [1].

Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications

The mobile TV applications such as DVH-H/T, T-DMB/DAB, ISDB-T are recently emerging all over the world. To support various applications, the multistandard and multiband mobile TV RF tuner is developed as a cost-effective and size-effective solution [1]. The demand for smaller form factor and power consumption reduction of RF and Channel is very high, and SoC technology is being adopted to meet the customers requirements. As shown in Fig. 25.7.1, an SoC that implements all of the standards and frequency bands of a mobile TV in a 65nm CMOS is presented in this paper. This RF SoC consists of three RF front ends, a dual-mode analog baseband filter supporting lowpass filtering and complex bandpass filtering, a digitally controlled programmable-gain amplifier (PGA), wideband VCO/PLL, DCXO, data converters, demodulator, forward error correction (FEC), hardwired multiprotocl encapsulation forward error correction (MPE-FEC), ARM CPU and SRAM. This mobile TV RF SoC reduces board area and complexity while cutting system design time.

2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power

A 12-bit 1.2V 160MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LSB respectively. The ADC shows a maximum SNDR of 58.5dB and 53.1dB and a maximum SFDR of 76.0dB and 67.8dB at 160MS/s and 200MS/s, respectively. The ADC with an active die area of 0.72mm2 shows a FoM of 0.75pJ/conv-step at 160MS/s and 1.2V.

A multistandard multiband mobile TV RF SoC in 65nm CMOS

A global system for mobile communications direct conversion receiver with an integrated synthesizer is implemented with a 0.35-mum BiCMOS technology. Proposed second-order intercept point calibration method is analyzed and verified by measurements. The maximum IIP2=66 dBm is achieved by an 8-b resistive calibration code. The receiver draws 57/63 mA from a 2.7-V supply