Ian A. Young

Optical I/O technology for tera-scale computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.

Optical technology for energy efficient I/O in high performance computing

Future high-performance computing systems will require optical I/O to achieve their aggressive bandwidth requirements of multiple terabytes per second with energy efficiency better than 1 pJ/b. Near-term optical I/O solutions will integrate optical and electrical components in the package, but longer-term solutions will integrate photonic elements directly into the CMOS chip to further improve bandwidth and energy efficiency. The presented near-term optical I/O uses a customized package to assemble CMOS integrated transceiver circuits, discrete VCSEL/detector arrays, and polymer waveguides. Circuit simulations predict this architecture will achieve energy efficiency better than 1 pJ/b at the 16 nm CMOS technology node. Monolithic photonic CMOS process technology enables higher bandwidth and improved energy efficiency for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides, and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator (RR) modulators and Ge detectors demonstrate performance at up to 40 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency of 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies with multilane communication or wavelength-division multiplexing will further increase bandwidth to provide the multiple-terabyte-per-second optical interconnect solution that enables scaling of high-performance computing into and beyond the tera-scale era.

A 0.35 /spl mu/m CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors

The clock frequency for microprocessors can be de-coupled from external logic and memory speed when a phase-locked loop (PLL) clock frequency generator is integrated on chip to synthesize the higher internal clock frequency from a lower frequency external system clock, and improve I/O timing by eliminating (deskewing) delay through the on-chip clock distribution network. Microprocessor clock frequencies are increasing faster than process technology performance improvement by reducing the number of gates between latches. This increases the ratio of flipflops or latches to logic gates, and together with the fact that approximately twice the number of logic gates are used with each new architecture, leads to significant increase in clock capacitive load and power. This trend also drives up the delay in distributing and buffering the clock around the microprocessor to more than 50% of the clock cycle. This work identifies and minimizes major contributions to jitter and skew in the complete clock generator that consists of a PLL operating with the distribution network, for a 203mm/sup 2/ 300MHz microprocessor.

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.

Optical I/O technology for digital VLSI

We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).

Optically Decoupled Loss Modulation in a Duo-Cavity VCSEL

We have proposed and demonstrated the principle of optical decoupling in a vertical-cavity surface-emitting laser (VCSEL)-electroabsorption modulator device by use of a duo-cavity device architecture. This technique promises ultrahigh-frequency modulation of the VCSEL output due to the elimination of the resonance influences on the intrinsic modulation transfer function. By adjusting spectral detuning between the resonances of the duo-cavity configuration, optical decoupling of output modulation by an electroabsorption modulator can be achieved. A flat ( 3 dB) response up to 20 GHz has been measured by proper detuning of the resonances.

Modulation Properties of VCSEL with Intracavity Modulator

We have studied the modulation properties of VCSEL with intracavity multiple quantum well (MQW) electroabsorption modulator integrated into the top distributed Bragg reflector (DBR) [1]. Small signal analysis of rate equations for loss modulation shows an intrinsic high-frequency roll-off slope of 1/&ohgr; instead of 1/&ohgr;2 in directly modulated laser diodes, and consequently bandwidths in excess of 40 GHz are obtainable with this configuration [2]. Possible limiting factors to high bandwidth were examined by fitting high frequency characteristics to a multi-pole transfer function, and include RC delay and carrier drift-limited time of flight (TOF) in the modulator intrinsic region. Intracavity loss modulation shows a strong (+20dB) relaxation oscillation resonant feature in both theory and experiment. As demonstrated, this feature can be significantly reduced in amplitude using parasitics. We have extracted relative contribution of TOF and parasitic capacitance by varying the modulator intrinsic region width (105 and 210 nm) and lateral size of the modulator (18 and 12&mgr;m). It was estimated that the small size modulator exhibits parasitics f-3dB at 8GHz. To estimate the carrier TOF contribution to bandwidth limits, low temperature growth of a 210 nm absorber i-region and MQW was employed to reduce photogenerated carrier lifetime. Bandwidth limitations were found to be mostly due to diode and metallization capacitances, in addition to one pole set by the optoelectronic resonance frequency. We have used p-modulation doping of the gain region to increase the relaxation frequency. Pronounced active Q-switching was observed, yielding pulse widths of 40 ps at a 4 GHz rate.

Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.

A replica-biased 50% duty cycle PLL architecture with 1/spl times/ VCO

A replica-biased PLL providing wider-frequency-range lower-power consumption and improved clock jitter and loop stability, is fabricated in 0.13/spl mu/m CMOS technology. A wide common-mode input range, matched-current amplifier provides a stable duty cycle at all operating conditions. In comparison of 1/spl times/ and 2/spl times/ VCO architecture, the 1/spl times/ VCO shows improved core timing.

Integration of nano-photonic devices for CMOS chip-to-chip optical I/O

This paper describes an optical interconnect solution based on a monolithic photonic CMOS architecture. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) photodetectors in a CMOS logic process. Experimental results for both the photonic CMOS ring resonator modulators and Ge detectors demonstrate 40 Gb/s performance.