Peter L. D. Chang

Optical I/O technology for tera-scale computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.

Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory

Key process features of a scaled, high-performance planar FBC memory fabricated on 25-nm undoped Si and 10-nm BOX SOI substrates are presented. Back-Gate (BG) doping process is revealed to be a critical part of the FBC integration. BG dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths (W<100 nm). Integrating BG doping processes and designing tips and source/drain, we demonstrate a memory retention of over 1 sec (@ 3-µA sensing window) in scaled cells (Lg=50 nm, W=85 nm) suitable for 15-nm technology node.

Floating Body Cell with Independently-Controlled Double Gates for High Density Memory

An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit better memory characteristics at a lower voltage than alternative FBC structures at comparable dimensions. Design, fabrication, operation, and scalability of IDG FBC devices are discussed

Electro-optic polymer cladding ring resonator modulators

Compact, low capacitance optical modulators are vital for efficient, high-speed chip to chip optical interconnects. Electro-optic (EO) polymer cladding micro-ring resonator modulators have been fabricated and their performance is characterized. Optical modulators with ring diameters smaller than 50 microm have been demonstrated in a silicon nitride based waveguide system on silicon oxide with a top cladding of an electro-optic polymer. Optical modulation has been observed with clock signals up to 10 GHz.

Optical technology for energy efficient I/O in high performance computing

Future high-performance computing systems will require optical I/O to achieve their aggressive bandwidth requirements of multiple terabytes per second with energy efficiency better than 1 pJ/b. Near-term optical I/O solutions will integrate optical and electrical components in the package, but longer-term solutions will integrate photonic elements directly into the CMOS chip to further improve bandwidth and energy efficiency. The presented near-term optical I/O uses a customized package to assemble CMOS integrated transceiver circuits, discrete VCSEL/detector arrays, and polymer waveguides. Circuit simulations predict this architecture will achieve energy efficiency better than 1 pJ/b at the 16 nm CMOS technology node. Monolithic photonic CMOS process technology enables higher bandwidth and improved energy efficiency for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides, and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator (RR) modulators and Ge detectors demonstrate performance at up to 40 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency of 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies with multilane communication or wavelength-division multiplexing will further increase bandwidth to provide the multiple-terabyte-per-second optical interconnect solution that enables scaling of high-performance computing into and beyond the tera-scale era.

A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond

A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX

A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and TIP implants are critical for achieving the balance between long retention time and large memory signal. For a minimum 3-muA sensing window, worst-case disturb retention of 25 ms is shown in scaled devices with 55 nm gate-length (LG) and 65 nm width (W). FBC scaling is predicted to be feasible at 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.

Floating-Body Diode—A Novel DRAM Device

A novel 8F2 DRAM cell is introduced, consisting of two gates controlling a low-doped silicon-on-insulator channel and opposite-polarity source and drain. Simulation with models calibrated to experimental floating-body cell data confirms virtual thyristor memory operation and demonstrates 85°C retention time in excess of 10 ms in a scaled FinFET architecture. With unit cell area comparable to that of conventional DRAM, 1.6-V total operation range, 1-ns program time, and CMOS-compatible process, floating-body diode is a candidate for stand-alone or embedded memory applications at 15-nm node and beyond.

Silicon on replacement insulator (SRI) floating body cell (FBC) memory

A 15-nm node floating body cell (FBC) memory was demonstrated utilizing silicon on replacement insulator (SRI) technology on bulk substrate. Highly selective SiGe etch and nano-scale anchors enabled the fabrication of silicon on thin replacement oxide of 12 nm. The memory characteristics show a memory signal of 7 µA and disturb retention time of 20 ms for a 51-nm gate length and 77-nm width device. This is the best FBC memory performance reported on bulk substrate.

Waveguide coupled Ge-on-oxide photodetectors for integrated optical links

We demonstrate Ge MSM photodetectors with responsivities of 0.9 A/W at 1310 nm and capable of data rates of 20 Gb/s. Direct Ge on oxide deposition makes these photodetectors potentially suitable for CMOS back-end optical links.