Miriam R. Reshotko

Optical I/O technology for tera-scale computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.

Electro-optic polymer cladding ring resonator modulators

Compact, low capacitance optical modulators are vital for efficient, high-speed chip to chip optical interconnects. Electro-optic (EO) polymer cladding micro-ring resonator modulators have been fabricated and their performance is characterized. Optical modulators with ring diameters smaller than 50 microm have been demonstrated in a silicon nitride based waveguide system on silicon oxide with a top cladding of an electro-optic polymer. Optical modulation has been observed with clock signals up to 10 GHz.

Optical technology for energy efficient I/O in high performance computing

Future high-performance computing systems will require optical I/O to achieve their aggressive bandwidth requirements of multiple terabytes per second with energy efficiency better than 1 pJ/b. Near-term optical I/O solutions will integrate optical and electrical components in the package, but longer-term solutions will integrate photonic elements directly into the CMOS chip to further improve bandwidth and energy efficiency. The presented near-term optical I/O uses a customized package to assemble CMOS integrated transceiver circuits, discrete VCSEL/detector arrays, and polymer waveguides. Circuit simulations predict this architecture will achieve energy efficiency better than 1 pJ/b at the 16 nm CMOS technology node. Monolithic photonic CMOS process technology enables higher bandwidth and improved energy efficiency for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides, and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator (RR) modulators and Ge detectors demonstrate performance at up to 40 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency of 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies with multilane communication or wavelength-division multiplexing will further increase bandwidth to provide the multiple-terabyte-per-second optical interconnect solution that enables scaling of high-performance computing into and beyond the tera-scale era.

Waveguide coupled Ge-on-oxide photodetectors for integrated optical links

We demonstrate Ge MSM photodetectors with responsivities of 0.9 A/W at 1310 nm and capable of data rates of 20 Gb/s. Direct Ge on oxide deposition makes these photodetectors potentially suitable for CMOS back-end optical links.

Challenges for on-chip optical interconnects

As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical building blocks will be reviewed. It will be shown that significant advances have been made in the design and fabrication of waveguides, detectors, and couplers. However, major challenges in high speed electrical to optical conversion and signaling remain.

High-speed CMOS-compatible photodetectors for optical interconnects

We have developed high-speed germanium (Ge) photodetectors using standard complementary metal-oxide-semiconductor (CMOS) process technology. We describe the design considerations that led to the devices reported on here. We have characterized these detectors in terms of the following detector metrics: speed, responsivity, dark current and capacitance. The photodetectors exhibit responsivities greater than 0.2 A/W at both 850 and 1550 nm, making them compatible with both long- and short-haul communication systems. Impulse response measurements at both of the above wavelengths indicate 3 dB cutoff frequencies greater than 10 GHz and open eye diagrams have been measured at 20 Gb/s. Dark currents are on the order of 10 to 1000 μA at a bias of 1 V depending on device size. Capacitances measured were on the order of 0.1-10 fF. The performance of the detectors indicates that they are suitable for high speed on-chip optical links. Device simulation models indicate that the fundamental upper limit on the speed of the devices, based on ideal material properties, is high enough to support a number of process generations. Calibration of the models to our experimental data is presented, and areas for improvement are defined.

A low power electro-optic polymer clad Mach-Zehnder modulator for high speed optical interconnects

Electro-optic (EO) polymer cladding modulators are an option for low-power high-speed optical interconnects on a silicon platform. EO polymers have inherently high switching speeds and have shown 40 Gb/s operation in EO polymer clad ring resonator modulators (RRM). In EO polymer clad RRM, the modulator’s area is small enough to be treated as a lumped capacitor; the capacitance is sufficiently low that the modulation speed is limited by the bandwidth of the resonator. A high Q resonator is needed for low voltage operation, but this can limit the speed and/or require precise control of the resonator’s wavelength, necessitating power consuming heaters to maintain optimal performance over a large temperature range. Mach Zehnder modulators (MZM), on the other hand, are not as sensitive to temperature fluctuations, but typically are relatively long and must employ power consuming terminated travelling wave electrodes. In this paper, a novel MZM design is presented using an EO polymer clad device. In this device, the electrodes are broken into short parallel segments and the waveguide folds around them. The segments of the electrode length are designed to provide good signal integrity up to 20 GHz without termination. The electrodes are driven by a single drive voltage and provide push-pull modulation. Modulators were designed and fabricated using silicon nitride waveguides on bulk silicon wafers and were demonstrated at high speed (20 GHz). A VπL as low as 1.7 Vcm is measured on initial devices. An optimized device could provide 40 Gb/s performance at 1 V drive voltages, ~100 fF total device capacitance and less than 2 dB optical insertion loss.

Integration of nano-photonic devices for CMOS chip-to-chip optical I/O

This paper describes an optical interconnect solution based on a monolithic photonic CMOS architecture. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) photodetectors in a CMOS logic process. Experimental results for both the photonic CMOS ring resonator modulators and Ge detectors demonstrate 40 Gb/s performance.

Surface plasmon induced polarization rotation and optical vorticity in a single mode waveguide.

The control and manipulation of the mode polarization state in a single mode dielectric waveguide is of considerable significance for optical information processing utilizing the polarization state to store digital information and integrated photonic devices used for high speed signaling. Here we report on an integrated on-chip mode polarization rotation based on short metal Cu electrodes placed in close proximity to the dielectric waveguide core. Polarization mode rotation with specific rotation of 10(4) degrees/mm is observed for offset metallic electrodes placed diagonally along a single mode dielectric waveguide. The mechanism for the polarization rotation is shown to be directional coupling into guided surface plasmon modes at the metal corners and coupling between the guided plasmon modes. This inter-plasmon coupling gives rise to giant polarization rotation and optical vorticity (helical power flow) in the waveguide.

Efficient and scalable single mode waveguide coupling on silicon based substrates

One of the key challenges in Silicon based optical interconnect system remains to be the efficient coupling of optical signals from the submicron size on-chip waveguides to standard single mode (SM) fibers with low insertion loss (IL) and relaxed alignment tolerance. Large optical alignment tolerance allows optical connectors to be attached to on-chip waveguides passively using standard semiconductor pick-and-place assembly tools that have placement accuracies of 10- 15μm. To facilitate the assembly, optical fiber coupling elements need to be modular and compact. They have to also have low profile to avoid blocking air flow or mechanical interference with other elements of the package. In this paper we report the development of a two-dimensional (2D) SM optical fiber coupling architecture that consists of Si based photonic lightwave circuit (PLC) substrate and a high-density micro-lensed fiber optic connector. The system is compact, efficient and has large optical alignment tolerance. At 1300nm an insertion loss of 2.4dB and 1.5dB was measured for the PLC module and the fiber optic connector, respectively. When the PLC module and connector was aligned together, a total insertion loss of 7.8dB was demonstrated with x,y alignment tolerance of 40μm for 1dB optical loss. The SM optical coupling architecture presented here is scalable, alignment tolerant and has the potential to be manufactured in high volume. To our knowledge, such a system has not been reported in the literature so far.