Ian Williams

An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

This paper presents an 8 channel energy-efficient neural stimulator for generating charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic Voltage Scaling (DVS). DC conversion efficiencies of up to 82% are achieved using integrated capacitances of under 1 nF and the DVS approach offers power savings of up to 50% compared to the front end of a typical current controlled neural stimulator. A novel charge balancing method is implemented which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Measured results indicate that the charge imbalance is typically between 0.05%-0.15% of charge injected for a series of pulses. Ex-vivo experiments demonstrate the viability in using this circuit for neural activation. The circuit has been implemented in a commercially-available 0.18 μm HV CMOS technology and occupies a core die area of approximately 2.8 mm2 for an 8 channel implementation.

Neuromodulation: present and emerging methods.

Neuromodulation has wide ranging potential applications in replacing impaired neural function (prosthetics), as a novel form of medical treatment (therapy), and as a tool for investigating neurons and neural function (research). Voltage and current controlled electrical neural stimulation (ENS) are methods that have already been widely applied in both neuroscience and clinical practice for neuroprosthetics. However, there are numerous alternative methods of stimulating or inhibiting neurons. This paper reviews the state-of-the-art in ENS as well as alternative neuromodulation techniques—presenting the operational concepts, technical implementation and limitations—in order to inform system design choices.

Live demonstration: A scalable 32-channel neural recording and real-time FPGA based spike sorting system

This demo presents a scalable a 32-channel neural recording platform with real-time, on-node spike sorting capability. The hardware consists of: an Intan RHD2132 neural amplifier; a low power Igloo® nano FPGA; and an FX3 USB 3.0 controller. Graphical User Interfaces for controlling the system, displaying real-time data, and template generation with a modified form of WaveClus are demonstrated.

An energy-efficient, dynamic voltage scaling neural stimulator for a proprioceptive prosthesis

This paper presents an energy-efficient neural stimulator capable of providing charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic Voltage Scaling (DVS). DC conversion efficiencies of between 63% and 76% are achieved using integrated capacitances of under 1nF and the DVS approach offers power savings of up to 53.5% compared to the front end of a typical current controlled neural stimulator. A novel charge balancing method is used which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Monte-Carlo simulations indicate that the charge imbalance can be less than 0.014% (at ±3σ) of charge delivered for a series of pulses. The circuit has been designed in a commercially-available 0.18µm HV CMOS technology and is estimated to require a die area of approximately 0.9mm2 for a 16 channel implementation.

An event-driven SoC for neural recording

This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs) and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Each channel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35 μm CMOS technology occupying a silicon area of 19.1 mm2 (0.3 mm2 gross per channel) and requiring 32 μW/channel power consumption (AFE only).

Improving neural spike sorting performance using template enhancement

This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the separation and variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.

A 32-ch. bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback

This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low-power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25 V, user-configurable amplitude (max. 315 μA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 μW per channel with programmable gain between 225–4725. Signals are 10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

Computationally efficient modeling of proprioceptive signals in the upper limb for prostheses: a simulation study

Accurate models of proprioceptive neural patterns could 1 day play an important role in the creation of an intuitive proprioceptive neural prosthesis for amputees. This paper looks at combining efficient implementations of biomechanical and proprioceptor models in order to generate signals that mimic human muscular proprioceptive patterns for future experimental work in prosthesis feedback. A neuro-musculoskeletal model of the upper limb with 7 degrees of freedom and 17 muscles is presented and generates real time estimates of muscle spindle and Golgi Tendon Organ neural firing patterns. Unlike previous neuro-musculoskeletal models, muscle activation and excitation levels are unknowns in this application and an inverse dynamics tool (static optimization) is integrated to estimate these variables. A proprioceptive prosthesis will need to be portable and this is incompatible with the computationally demanding nature of standard biomechanical and proprioceptor modeling. This paper uses and proposes a number of approximations and optimizations to make real time operation on portable hardware feasible. Finally technical obstacles to mimicking natural feedback for an intuitive proprioceptive prosthesis, as well as issues and limitations with existing models, are identified and discussed.

Compact standalone platform for neural recording with real-time spike sorting and data logging

OBJECTIVE Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. APPROACH We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. MAIN RESULTS The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. SIGNIFICANCE The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable output suitable for BMIs, closed loop neuromodulation, wireless transmission and long term data logging.

Fiber size-selective stimulation using action potential filtering for a peripheral nerve interface: A simulation study

Functional electrical stimulation is a powerful tool for restoration of function after nerve injury. However selectivity of stimulation remains an issue. This paper presents an alternative stimulation technique to obtain fiber size-selective stimulation of nerves using FDA-approved electrode implants. The technique was simulated for the ventral roots of Xenopus Laevis, motivated by an application in bladder control. The technique relies on applying a high frequency alternating current to filter out action potentials in larger fibers, resulting in selective stimulation of the smaller fibers. Results predict that the technique can distinguish fibers with only a 2 μm difference in diameter (for nerves not exceeding 2mm in diameter). The study investigates the behaviour of electrically blocked nerves in detail. Model imperfections and simplifications yielded some artefacts in the results, as well as unexpected nerve behaviour which is tentatively explained.