Iasson Vassiliou

Behavioral simulation techniques for phase/delay-locked systems

This paper presents behavioral simulation techniques for phase/delay-locked systems. Numerical simulation algorithms are compared and the issue of numerical noise is discussed. Behavioral phase noise simulation for phase/delay-locked systems is described. The role of behavioral simulation for phase/delay-locked systems in our top-down constraint-driven design methodology, and in bottom-up verification of designs, is explained with examples. Accuracy and efficiency comparisons with other methods are made. Simulation techniques are described in the framework of phase/delay-locked systems, but simulation methodology and the results attained in this work are applicable to the behavioral simulation of mixed-mode nonlinear dynamic systems.<<ETX>>

A frequency-domain, Volterra series-based behavioral simulation tool for RF systems

In this paper a new behavioral modeling approach for RF systems based is presented, based on a Volterra series input-output map representation. The modeling is done purely in the frequency domain, capturing the typical system level specifications for RF building blocks, independent of the implementation details. A harmonic balance simulation tool has been developed based on those models. The implementation focuses on deterministic effects such as distortion and frequency conversion. The behavioral simulator has been tested for various systems and results are presented.

A video driver system designed using a top-down, constraint-driven methodology

To accelerate the design cycle for analog and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. The key idea of the proposed methodology is hierarchically propagating constraints from performance specifications to layout. Consequently, it is essential to provide the necessary tools and techniques enabling the efficient constraint propagation. To illustrate the applicability of the proposed methodology to the design of larger systems, we present in this paper the complete design flow for a video driver system. Critical advantages of the methodology illustrated with this design example include avoiding costly low level re-designs and getting working silicon parts from the first run. Following our approach, a jitter constraint is imposed at the system level and then is propagated hierarchically to the circuit blocks and layout, using behavioral modeling and simulation. Experimental results are presented from working fabricated parts.

Use of sensitivities and generalized substrate models in mixed-signal IC design

A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal. Circuits in presence of layout parasitics and substrate induced noise. Accurate and efficient evaluation of the circuit during design is possible by taking into account such non-idealities. Techniques are presented to derive and use a set of constraints on substrate noise and on the geometric instances of the layout. Verification is performed using substrate extraction in combination with parasitic estimation techniques. To show the suitability of the approach, a VCO for a PLL has been designed and implemented in a CMOS 1 /spl mu/m technology. The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensitivity to layout parasitics and substrate noise has been minimized.

Σ-Δ Analog-To-Digital Converter Design Example

This Σ-Δ A/D design example is the second in a series of design examples that we take through fabrication. We show that even though the circuits arid architecture are different from the ones in the first example, the methodology is applied in the same way. The two examples significaiitly differ for the following reasons: (1) the subcomponents are different, (2) the overall performance specifications and the reasons for their degradation are different, and (3) the sub-blocks are not in regular arrays. Its relative level of complexity is shown in Figure 9.1.

Video Driver Design Example

The design of a video driver system is the last example in our current set. New behavioral modeling, optimization, and layout techniques have beeti developed or extended from existing ones, in order to provide a full set of tools supporting the design of a class of similar mixed-signal systems. This description focuses on the “critical path” of the design. At the high-level synthesis phase, emphasis is given at the PLL behavioral models and simulation techniques. The setup of the PLL optimization problem that performs the constraint mapping, together with the appropriate optimization algorithm are also described. The novelty of the design approach includes a jitter constraint which is set at the system level and mapped onto circuit level constraints. Typically, simulation (if any, and usually only at the circuit level) is used to verify the performance at the bottom of the hierarchy, thus causing expensive design iterations. Following the “critical path” of the design, the VCO synthesis phase is depicted, with focus on the optimization approach that takes into account layout parasitics. The layout constraints generated at the circuit level are enforced during the VCO layout synthesis phase. Finally, detailed extraction of the sub-blocks and behavioral system-level simulation is used for the verification of the system performance for the PLL.

Simulation and Behavioral Modeling

Simulation with accurate and realistic models has been an invaluable tool for the verification of the electrical performance of integrated circuits. Simulators hold a particularly important place in the world of analog and mixed-signal design tools. Primarily, they verify that the circuit as designed will perform as expected. They are also used in design space exploration. It is most important that a simulator be trustworthy, but it is also important that the simulator be fast and robust. When designing very high-performance circuits, accurate prediction of the time and frequency-domain behavior of the circuit is needed. Such prediction can only be achieved by the use of circuit simulators that analyze detailed waveforms. These simulators (e.g. SPICE [217][248]) can provide accurate results, but sometimes at the expense of very long (possibly unaffordable) computing time. In particular, when complex analog and mixed-signal systems are being designed, accurate circuit simulation of the entire circuit is out of the question. The complexity in terms of the number of components, and of the types of analyses makes the use of SPICE too time consuming. Moreover, it may not be possible to use a circuit simulator to make design “decisions” at the “higher” levels in a top-down design process, because the detailed circuit implementations of the sub-blocks may not be available at that particular level of the design hierarchy.

Constraint-Driven Layout Synthesis

Research on CAD systems for reliable physical assembly of analog circuits has progressed at a considerably slower pace than that for digital counterparts. Part of the reason has been the intrinsic difficulty of defining and controlling performance in analog circuits. High performance can be achieved by talcing advantage of the physical characteristics of integrated devices and of the correlation between electrical parameters and their variations due to statistical fluctuations of the manufacturing process. Device matchings, parasitics, thermal and substrate effects must all be taken into account. The nominal values of performance functions are subject to degradation due to a large number of parasitics which are generally difficult to estimate accurately before the actual layout is completed.

Current Source Digital-To-Analog Converter Design Example

Presented in this chapter is the first of a series of industrial strength design examples of increasing levels of design complexity to illustrate the methodology and to show its effectiveness. Design complexity is difficult to quantify, because there are many factors to consider, e.g, designer level of expertise, availability of tools, and aggressiveness of performance specifications desired. However, to show where our examples fit into the “big picture,” an attempt is made to rank complexity levels in Figure 9.1. Our first example, current source D/As, falls somewhere in the mid-range for analog circuits.

Architectural Mapping and Optimization

Once a behavioral simulator has been developed, the next step in the development of the design methodology is in its application to architecture mapping. One key contribution of this work is to define a mechanism by which hierarchy can be exploited successfully. The example in Figure 4.1 will be used to illustrate this.