Enrico Malavasi

Automation of IC layout with analog constraints

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

Design of mixed-signal systems-on-a-chip

The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

A Constraint-driven Placement Methodology For Analog Integrated Circuits

A new constraint-driven methodology for the placeinent of analog ICs is described. Electrical performance specifications are automatically translated into constraints on the layout parasitics. These constraints and the seiisiitivity iiiforinatioii of the circuit are then used to control a Simulated Annealingbased placement algorithm. At each step of the annealing a fast check on performance degradations is performed to guarantee that the tool has the necessary robur,tness.

Area routing for analog layout

An area router specifically tailored for the layout of analog circuits is presented. It is based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable cost function based on a set of user-defined weights. The weights can be automatically defined based on high-level electrical performance specifications and determine the net scheduling. An algorithm for symmetric routing preserves symmetries in differential architectures. Different current paths can be dealt with in each wire by means of a net partitioning procedure driven by information on the current driven by terminals. Shields can be built between critically coupled wires, in order to guarantee an effective limitation of cross-coupling. The weight-driven programmable cost function makes this router particularly suitable for a performance-driven approach to analog routing. Automatic weight definition also makes the use of the tool independent of the users expertise. The implemented algorithms are described, and results proving the effectiveness of this approach are given. >

Generalized constraint generation for analog circuit design

A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information.

A routing methodology for analog integrated circuits

A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described. In this approach, sensitivities of performance to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performance are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated with the parasitics which violated the constraints, and the circuit is rerouted. Results validating the effectiveness of this approach for layout-design automation of analog circuits are reported.<<ETX>>

Enhanced network flow algorithm for yield optimization

A novel constraint-graph algorithm for the optimization of yield is presented. This algorithm improves the yield of a layout by carefully spacing objects to reduce the probability of faults due to spot defects. White space between objects is removed and spacing in tightly packed areas of the layout is increased. The computationally expensive problem of optimizing yield is transformed into a network flow problem, which can be solved via known efficient algorithms. Yield can be improved either without changing the layout area, or if necessary by increasing the layout area to maximize the number of good chips per wafer. Our method can in theory provide the best possible yield achievable without modifying the layout topology. The method is able to handle a general class of convex objective functions, and can therefore optimize not only yield, but other circuit performance functions such as wire-length, cross-talk and power.

Performance-driven compaction for analog integrated circuits

The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.

An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints

An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allow the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints.<<ETX>>

Top-down, constraint-driven design methodology based generation of n-bit interpolative current source D/A converters

To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. In this paper we present a design which demonstrates the two principal advantages that this methodology provides- a high probability for first silicon which meets all specifications and fast design times. We examine the design of three different 10-bit digital-to-analog (D/A) converters beginning from their performance and functional specifications and ending with the testing of the fabricated parts. Critical technology mismatch information gathered from the testing phase is provided.<<ETX>>