Umakanta Choudhury

Automatic generation of analytical models for interconnect capacitances

An analytical-model generator for interconnect capacitances is presented. It obtains analytical expressions of self and coupling capacitances of interconnects for commonly encountered configurations, based on a series of numerical simulations and a partial knowledge of the flux components associated with the configurations. The configurations which are currently considered by this model generator are: (a) single line; (b) crossing lines; (c) parallel lines on the same layer; and (d) parallel lines on different layers (both overlapping and nonoverlapping). >

A Constraint-driven Placement Methodology For Analog Integrated Circuits

A new constraint-driven methodology for the placeinent of analog ICs is described. Electrical performance specifications are automatically translated into constraints on the layout parasitics. These constraints and the seiisiitivity iiiforinatioii of the circuit are then used to control a Simulated Annealingbased placement algorithm. At each step of the annealing a fast check on performance degradations is performed to guarantee that the tool has the necessary robur,tness.

Constraint generation for routing analog circuits

An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.

Constraint-based channel routing for analog and mixed analog/digital circuits

A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges, and increasing the weights of edges in the VC graph in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments while attempting to cause minimum increase in the channel height due to the constraints. Use is made of shield nets when necessary. A formal description of the conditions under which the crossover and the adjacency constraints are satisfied is provided and used to construct the appropriate mapping algorithms. The problem of imposing matching constraints on the routing parasitics in a channel with lateral symmetry is addressed. It is observed that perfect matching is not possible for a matched pair of nets with intersecting horizontal spans. A technique to achieve almost perfect mirror symmetry is presented for such pairs of nets. >

Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits

A design methodology for the physical design of analog circuits is proposed. The methodology is based on the automatic generation of constraints on parasitics introduced during the layout phase from constraints on the functional performance of the circuit. In this novel performance-constrained approach, the parasitic constraints drive the layout tools to reduce the need for further layout iterations. Parasitic constraint generation involves (1) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the layout tools while meeting the performance constraints; and (2) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. The constraint generator PARCAR is described and results presented for test circuits. >

A routing methodology for analog integrated circuits

A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described. In this approach, sensitivities of performance to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performance are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated with the parasitics which violated the constraints, and the circuit is rerouted. Results validating the effectiveness of this approach for layout-design automation of analog circuits are reported.<<ETX>>

An analytical-model generator for interconnect capacitances

A tool for automatically generating analytical models of interconnect capacitances is presented. It uses a partial knowledge of the flux components associated with a configuration to choose a suitable form of analytical expression, and then uses curve-fitting techniques to obtain the analytical models. For each coupled configuration, the form for the coupling capacitance is chosen based on a decomposition of the mutual flux associated with the two lines. The form for the correction capacitance of each line is decided based on a decomposition of its flux intercepted by the other line. A design-parameter-based modeling is pursued, since often it is desired to perform a large number of evaluations of a capacitance in a layout, with a fixed set of process parameters, but for varying values of design parameters. The configurations which are currently considered by this model generator are a single line, crossing lines, parallel lines on the same layer, and parallel lines on different layers (both overlapping and nonoverlapping).<<ETX>>

General AC constraint transformation for analog ICs

The problem of designing complex analog circuits is attacked using a hierarchical top-down, constraint-driven design methodology. In this methodology, constraints are propagated automatically from high-level specifications to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which specifications are met. In this paper we describe how constraint transformations can be efficiently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex high-level specification handling and accounts for second-order effects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4th order active filter test case.

A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits

This paper describes a top-down, constraint-driven design methodology for analog integrated circuits. Some of the tools that support this methodology are described. These include behavioral simulation tools, tools for physical assembly, and module generators. Finally, examples of behavioral simulation with optimization and physical assembly are provided to better illustrate the methodology and its integration with the tool set.