Eric Felt

Automation of IC layout with analog constraints

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling

A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.

Measurement and modeling of MOS transistor current mismatch in analog IC's

This paper presents a new methodology for measuring MOS transistor current mismatch and a new transistor current mismatch model. The new methodology is based on extracting the mismatch information from a fully functional circuit rather than on probing individual devices; this extraction leads to more efficient and more accurate mismatch measurement. The new model characterizes the total mismatch as a sum of two components, one systematic and the other random. For our process, we attribute nearly half of the mismatch to the systematic component, which we model as a linear gradient across the die. Furthermore, we present a new model for the random component of the mismatch which is 60% more accurate, on average, than existing models.

Dynamic variable reordering for BDD minimization

Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested.<<ETX>>

Analog testability analysis and fault diagnosis using behavioral modeling

This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models. A key contribution is a new algorithm for determining analog testability. Experimentally, we determined the testability and faults of a fabricated 10 bit digital-to-analog converter modeled using the analog hardware description language, Cadence-AHDL. Also, we applied the testability analysis at the circuit level using SPICE sensitivity analysis.<<ETX>>

Performance-driven compaction for analog integrated circuits

The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.

An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints

An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allow the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints.<<ETX>>

Top-down, constraint-driven design methodology based generation of n-bit interpolative current source D/A converters

To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. In this paper we present a design which demonstrates the two principal advantages that this methodology provides- a high probability for first silicon which meets all specifications and fast design times. We examine the design of three different 10-bit digital-to-analog (D/A) converters beginning from their performance and functional specifications and ending with the testing of the fabricated parts. Critical technology mismatch information gathered from the testing phase is provided.<<ETX>>

Top-down, constraint-driven design methodology based generation of a second order /spl Sigma/-/spl Delta/ A/D converter

To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. In this paper we present a complete design flow to illustrate this design methodology as it applies to the design of a second order sigma-delta (/spl Sigma/-/spl Delta/) analog-to-digital (A/D) converter. We start from its performance and functional specifications and ending with the testing of the fabricated parts. Experimental results are presented.

Testing of analog systems using behavioral models and optimal experimental design techniques

This paper describes a new CAD algorithm which performs automatic test pattern generation (ATPG) for a general class of analog systems, namely those circuits which can be efficiently modeled as an additive combination of user-defined basis functions. The algorithm is based on the statistical technique of I-optimal experimental design, in which test vectors are chosen to be maximally independent so that circuit performance will be characterized as accurately as possible in the presence of measurement noise and model inaccuracies. This technique allows analog systems to be characterized more accurately and more efficiently, thereby significantly reducing system test time and hence total manufacturing cost.