Ichiro Mori

Piezoelectrically Driven xyθ Table for Submicron Lithography Systems

A newly designed piezoelectrically driven XYθ table has been developed for submicron lithography systems. The XYθ table was fabricated using a monolithic plate structure, joined together with flexure hinges and driven by an inchworm function. This function involves the periodic clamping and unclamping of four blocks and the expansion and contraction of piezoelectric actuators. The XYθ table can travel a long distance with fine positioning in the X, Y, and θ directions. The velocities can be controlled up to 0.5 mm/s in the X and Y directions, and 0.3×10 −2 rad/s in the θ direction by changing the inchworm function stepping rate. Positioning accuracy of less than 1 μm in the X and Y directions, and 7.5×10−6 rad in the θ direction can easily be obtained using a servo system with a 0.5‐μm measuring resolution.

Beam induced deposition of an ultraviolet transparent silicon oxide film by focused gallium ion beam

We have deposited a silicon oxide (SiOx) film with a high optical transmittance in the DUV region by a focused ion beam induced deposition technique using a gallium ion beam and a mixture of oxygen and TMCTS(1,3,5,7‐tetramethylcyclotetrasiloxane) as a source gas. The optical transmittance of a 0.3 μm thick film is higher than 90% at the wavelength of 250 nm. The transmittance of the deposited SiOx film depends on both the source gas and ion beam irradiation conditions. A scaling to explain the transmittance along with the ion beam conditions is proposed.

Optimization of optical properties for single-layer halftone masks

An algorithm necessary to decide the optimum optical properties of a single-layer halftone (HT) mask has been established. This paper reveals the relations between the refractive index n and the extinction coefficient k, and thickness d, and describes how to select optimum films among various materials. It has been found that SiNx is a good material for a single-layer HT mask for I-line (365 nm) and KrF (248 nm). The lithographic performance of an I-line SiNx HT mask for grouped line and space (L&S) patterns under annular illumination has also been demonstrated.

A study of radiation damage in SiN and SiC mask membranes

Radiation damage in SiN and SiC films prepared by low‐pressure chemical vapor deposition (LPCVD) is reported. A pattern placement error of 0.05 μm at the edge of the x‐ray radiation area was introduced for SiN membranes by a radiation dose of 12 kJ/cm2. The electron spin resonance (ESR) signals with a g value of 2.004, which was attributed to the Si–N dangling bond, were observed. Both the error and the spin density increased with increasing radiation dose up to 12 kJ/cm2 and remained constant thereafter. The error was explained as the result of Si–N bond scission caused by x‐ray radiation, leading to tensile stress relaxation in the radiated area. In the case of SiC films, a pattern placement error was less than a detection limit of 0.03 μm for a radiation dose of 10 kJ/cm2. ESR signals with a g value of 2.003, being attributed to the Si–C dangling bond, were observed. However, the spin density in this case did not change by radiation up to 20 kJ/cm2. It is inferred that the LPCVD SiC membrane is damage ...

Flexible mask specifications

As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing. This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.

Yield-enhanced layout generation by new design for manufacturability (DfM) flow

Design for manufacturability ( DfM ) flow consisting of a new lithography design approach at the design rule definition stage and manufacturability check at physical layout stage is proposed to clean up hot spots and guarantee the final layouts to be free of hot spots under low-k1 lithography condition. At the initial development stage, design rules ( DRs ), resolution enhancement technique ( RET ) and optical proximity correction ( OPC ) methods and critical dimension ( CD ) target and specification are determined by the new lithography design approach to reduce hot spots next-generation’s tentative layout made by the compactor. At the physical layout stage, a manufacturability check ( MC ) is essential to wipe out hot spots resulted from immaturity of DRs and process parameters fixed at the initial development stage by making three feedback approaches: the refinement of design rule, the repair of hot spots by designers and the refinement of OPC parameters and/or methods. Also, an alternative of layout modification or OPC improvement for cleaning hot spots are cleared by categorization of CD variation induced by some dose and focus conditions and an error of CD average for the target pattern. The proposed DfM flow is found to be highly effective for the robust pattern formation under the low-k1 lithography condition.

Maskless lithography: a low-energy electron-beam direct writing system with a common CP aperture and the recent progress

In order to realize SoC (System on a Chip) fabrication at low cost with quick-TAT (Turn-Around-Time) we have proposed a maskless lithography (ML2) strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This paper presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a SEM function of LEEBDW system is also reported.

Maskless lithography using low-energy electron beam: Recent results for proof-of-concept system

In order to realize a system on a chip fabrication at low cost with quick turn-around-time, we have proposed a maskless lithography strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This article presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting of small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50-nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a scanning electron microscope function of LEEBDW system is also reported.

Process liability evaluation for EUVL

This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

Flare compensation for EUVL

At Selete, correction for flare based on a flare point-spread function (PSFF) is investigated. We divide a layout into a grid and calculate pattern density for each grid square, obtaining a density array as an approximation to the layout aerial image. Then, the density array is convolved with the PSFF to create an array of flare values. Using this flare-value array, we resize the layout. In the above correction flow, size of a grid square of density array and a selection of an approximate function of the PSFF have a great influence on the accuracy of flare value computation. In this study, correction for flare was applied to the fabrication of several test masks using the real PSFF obtained from a full-field step-and-scan exposure tool called EUV1. We report on the optimization of size of grid square, on a suitable approximation model of PSFF, and on feedbacks from exposure experiments.