Kazuyoshi Sugihara

Fabrication of Silicon-on-Nothing Structure by Substrate Engineering Using the Empty-Space-in-Silicon Formation Technique

A practical method for the fabrication of a silicon on nothing (SON) structure with the desired size and shape has been developed by using the empty-space-in-silicon (ESS) formation technique. It was found that the SON structure could be precisely controlled by the initial shape and layout of the trenches. The size of ESS is determined by the size of the initial trench. The desired shapes of ESS, such as spherical, pipe-shaped and plate-shaped, can be fabricated by changing the arrangement of the initial trenches. The fabricated SON region over ESS has excellent crystallinity adoptable for ultra-large-scale integrated circuit (ULSI) applications. The SON structure would be a promising substrate structure for various manufacturing technologies, such as the micro-electro-mechanical system (MEMS), photonic crystals and waveguides.

Piezoelectrically Driven xyθ Table for Submicron Lithography Systems

A newly designed piezoelectrically driven XYθ table has been developed for submicron lithography systems. The XYθ table was fabricated using a monolithic plate structure, joined together with flexure hinges and driven by an inchworm function. This function involves the periodic clamping and unclamping of four blocks and the expansion and contraction of piezoelectric actuators. The XYθ table can travel a long distance with fine positioning in the X, Y, and θ directions. The velocities can be controlled up to 0.5 mm/s in the X and Y directions, and 0.3×10 −2 rad/s in the θ direction by changing the inchworm function stepping rate. Positioning accuracy of less than 1 μm in the X and Y directions, and 7.5×10−6 rad in the θ direction can easily be obtained using a servo system with a 0.5‐μm measuring resolution.

Throughput enhancement strategy of maskless electron beam direct writing for logic device

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P and R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

Beam induced deposition of an ultraviolet transparent silicon oxide film by focused gallium ion beam

We have deposited a silicon oxide (SiOx) film with a high optical transmittance in the DUV region by a focused ion beam induced deposition technique using a gallium ion beam and a mixture of oxygen and TMCTS(1,3,5,7‐tetramethylcyclotetrasiloxane) as a source gas. The optical transmittance of a 0.3 μm thick film is higher than 90% at the wavelength of 250 nm. The transmittance of the deposited SiOx film depends on both the source gas and ion beam irradiation conditions. A scaling to explain the transmittance along with the ion beam conditions is proposed.

Ion-graphy implanter with stencil mask

Recently, the demand for semiconductor devices has been greatest in the consumer market for such products as video games, cellular phones, and DVD players. In order to satisfy these demands, semiconductor manufacturers are now designing new production lines, such as mini fabs, to decrease the processing time for various types of semiconductor devices. Over the past few decades, the availability and throughput of ion implanters have improved dramatically. However, the implantation process itself has, except for a slight change, remained basically the same. A recent article (Ref. 1) describes the basic concept of an ion-implantation process that does not require use of a photoresist mask. This article reports the experimental data and the basic functions of a type of ion implanter currently being developed. This implanterimplants ions in one chip at a time through a stencil mask without the use of a photoresist mask. This ion-implantation technology, called stencil mask ion implantation technology, and the ion implanter, called a stencil mask lithographic ion implanter, will be exceptionally suitable for future semiconductormanufacturing processes.

Stencil mask ion implantation technology

The ion implantation process is important for the development or manufacturing of semiconductor devices, because ion implantation conditions directly influence some characteristics of semiconductor devices. Recently, we developed a new implantation technology, stencil mask ion implantation technology (SMIT). In the SMIT system, the stencil mask acts like a resist mask, and ions passing through the mask holes are implanted into selected regions of the Si substrate chip by chip. Use of SMIT has several advantages, notably lower manufacturing cost and shorter process time than in the case of conventional processing, because no photolithography process (including deposition and stripping of resist) is required. We have already demonstrated an application of SMIT to transistor fabrication, using various implanted dose conditions for the same wafer. Threshold voltage values can be controlled as effectively by implanted doses as they can by conventional implantation, and the dose dependence of the threshold voltage could be obtained from one wafer to which various implantation conditions are applied. Using SMIT, implantation conditions can be changed chip by chip without additional processes. This flexibility of implantation conditions is another advantage of SMIT. In this paper, we propose stencil mask ion implantation technology and show some fundamental results obtained by applying SMIT.

Alignment system using voltage contrast images for low-energy electron-beam lithography

We have proposed an alignment system for low-energy electron-beam lithography. The proposed alignment system is based on the following unique concepts: (1) an alignment mark is detected using voltage contrast images caused by charging, and (2) to improve the alignment accuracy of global alignment, the alignment accuracy can be inspected before the pattern exposure without any loss of time. In order to verify these concepts, we performed a series of experiments. Using an electron beam of a few keV, we detected a mark buried by thick insulator films; even if direct access to the marks by the primary beam is prevented, the mark detection is possible. Also, we confirmed that the simultaneous observation of exposure patterns and alignment mark is possible using the voltage contrast images caused by charging: the inspection is possible for the exposure status without resist development.

Maskless lithography: a low-energy electron-beam direct writing system with a common CP aperture and the recent progress

In order to realize SoC (System on a Chip) fabrication at low cost with quick-TAT (Turn-Around-Time) we have proposed a maskless lithography (ML2) strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This paper presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a SEM function of LEEBDW system is also reported.

Edge Roughness Study of Chemically Amplified Resist in Low-Energy Electron-Beam Lithography Using Computer Simulation

We investigated the line edge roughness (LER) of chemically amplified resist (CAR) in the high-sensitivity resist process in low-energy electron beam lithography (LEEBL). We have confirmed that a sub-100 nm pattern having a small line edge roughness could be obtained at the exposure dose below sub-1 µC/cm2 for LEEBL. In order to explain the experimental results, we have proposed a resist exposure model, considering the generation yield and diffusion of secondary electrons (SEs). Based on the proposed model, we analyzed the LER for LEEBL using a simulation. When the beam blur and the acceptable LER were 30 nm (σ) and 2 nm (σ), the acceptable exposure doses for 2–5 keV and 50 keV were 0.3 µC/cm2 and 2.5 µC/cm2, respectively. This means that a high-sensitivity CAR process at the exposure dose below 0.5 µC/cm2 can be achieved in LEEBL.

New registration technique using voltage-contrast images for low-energy electron-beam lithography

We have developed a new registration technique for low energy electron beam lithography. A notable feature of this technique is the use of voltage contrast images caused by charging at the resist surface. Using the electron beam of incident energy range of 1keV to 4.5keV, we detected the mark buried by thick insulator films; even if direct access tot he marks by the primary beam is prevented, the mark detection is possible. The detection time is a few milliseconds, and it is sufficiently fast. We confirmed that this technique is available for various layers of DRAM. Also the possible mechanism that may explain the voltage contrast image caused by negative charging is discussed.