Idongesit Ebong

Nanoscale Memristor Device as Synapse in Neuromorphic Systems

A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal-oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.

CMOS and Memristor-Based Neural Network Design for Position Detection

Most hardware neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights two basic learning rules/behavior: winner-take-all (WTA) and spike-timing-dependent plasticity (STDP). It also gives a design example implementing WTA combined with STDP in a position detector. A complementary metal-oxide-semiconductor (CMOS) and a memristor-MOS technology (MMOST) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout were done in 130-nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes area, 55-W max power, and requires a 3-dB SNR. On the other hand, the MMOST design consumes , 15-W max power, and requires a 4.8-dB SNR. There is a potential to improve upon analog computing with the adoption of MMOST designs.

Self-Controlled Writing and Erasing in a Memristor Crossbar Memory

The memristor device technology has created waves in the research community and led to the consideration of using the device in multiple avenues. The most likely candidate for early adoption is the nonvolatile memory due to the small cell size (increased scaling potential), increased density as compared to flash, and ability to stack these devices in a crossbar structure. This paper analyzes the feasibility of a memristor memory and introduces an adaptive read, write, and erase method that may be used to realize a more resilient memory system in the face of low yield in the nanotechnology regime. The proposed method is evaluated in simulation program with integrated circuit emphasis (SPICE) and a hand analysis model is extracted to help explain the sources of power and energy consumption. Finally, the power metrics are compared to flash memory technology, and the memristor memory is shown to have an energy per bit consumption about one-tenth that of flash when programming, comparable to flash when erasing, and about one-fourth of flash when reading.

Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing

The resonant tunneling diode (RTD) has found numerous applications in high-speed digital and analog circuits due to the key advantages associated with its folded back negative differential resistance (NDR) current-voltage (I-V) characteristics as well as its extremely small switching capacitance. Recently, the RTD has also been employed to implement high-speed and compact cellular neural/nonlinear networks (CNNs) by exploiting its quantum tunneling induced nonlinearity and symmetrical I-V characteristics for both positive and negative voltages applied across the anode and cathode terminals of the RTD. This paper proposes an RTD-based CNN architecture and investigates its operation through driving-point-plot analysis, stability and settling time study, and circuit simulation. Full-array simulation of a 128 times 128 RTD-based CNN for several image processing functions is performed using the Quantum Spice simulator designed at the University of Michigan, where the RTD is represented in SPICE simulator by a physics based model derived by solving Schrodingers and Poissons equations self-consistently. A comparative study between different CNN implementations reveals that the RTD-based CNN can be designed superior to conventional CMOS technologies in terms of integration density, operating speed, and functionality.

Memristor based STDP learning network for position detection

Most neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights three basic learning rules - winner-take-all (WTA), spike timing dependent plasticity (STDP), and inhibition of return (IOR). It also gives a design example implementing WTA combined with STDP in a position detector. A CMOS and an MMOST (Memristor-MOS Technology) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout was done in 130 nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes 2.9×10−4cm2 area, 55 µW max power, and requires a 3 dB SNR. On the other hand, the MMOST design consumes 6×10−5cm2, 15 µW max power, and requires a 4.8 dB SNR.

Digital implementation of a virtual insect trained by spike-timing dependent plasticity

Neural network approach to processing have been shown successful and efficient in numerous real world applications. The most successful of this approach are implemented in software but in order to achieve real-time processing similar to that of biological neural networks, hardware implementations of these networks need to be continually improved. This work presents a spiking neural network (SNN) implemented in digital CMOS. The SNN is constructed based on an indirect training algorithm that utilizes spike-timing dependent plasticity (STDP). The SNN is validated by using its outputs to control the motion of a virtual insect. The indirect training algorithm is used to train the SNN to navigate through a terrain with obstacles. The indirect approach is more appropriate for nanoscale CMOS implementation synaptic training since it is getting more difficult to perfectly control matching in CMOS circuits.

Multi-purpose neuro-architecture with memristors

An analog CMOS neuromorphic design utilizing spike timing dependent plasticity and memristor synapses is investigated for use in building a multi-purpose analog neuromorphic chip. In order to obtain a multi-purpose chip, a suitable architecture is established and several functions with the proposed architecture are shown. Using the IBM 90 nm CMOS9RF process, neurons are designed to interface with Verilog-A memristor synapse models to perform the XOR and Edge Detection functions.

Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques

Different techniques of power savings in CMOS circuits have been investigated through the years. This work compares the asynchronous approach, the superthreshold approach, and the subthreshold approach in a 128 point FFT processor. The subthreshold design, made in TSMC 65 nm technology, utilizes a 4 kb SRAM with 8T unit cells. The sizing requirements for the 8T cell operated in subthreshold regime is explored as a function of static write margin. The subthreshold processor runs at 1 MHz with an energy consumption of 31 nJ/FFT. Subthreshold approach is seen to be the most energy efficient low power method of the three approaches.

Iterative architecture for value iteration using memristors

Memristors promise higher device density and design flexibility. Besides utilizing memristors for digital memory, another promising avenue for adoption is the advancement of neural network circuits capable of learning. Neural network implementations with memristors have been proposed, including memristor synaptic training methodologies. This work highlights applications of a neural learning methodology inspired by Q-learning. Memristors are used as analog storage elements to store a large Q-table. The method is qualified with a maze problem in order to show that the proposed network can be used to learn to approximate an optimal path to solving the maze problem. Brief results highlighting the methodology on a maze problem and discussion on generating random keys are provided. This work combines model-free reinforcement learning with neural networks.