Igor Kleyner

The effects of architecture and process on the hardness of programmable technologies

Architecture and process, combined, significantly affect the hardness of programmable technologies. The effects of high energy ions, ferroelectric memory architectures, and shallow trench isolation are investigated. A detailed single event latchup (SEL) study has been performed.

Science of opportunity: Heliophysics on the FASTSAT mission and STP-S26

The FASTSAT spacecraft, which was launched on November 19, 2010 on the DoD STP-S26 mission, carries three instruments developed in joint collaboration by NASA GSFC and the US Naval Academy: PISA, TTI, and MINI-ME.1,2 As part of a rapid-development, low-cost instrument design and fabrication program, these instruments were a perfect match for FASTSAT, which was designed and built in less than one year. These instruments, while independently developed, provide a collaborative view of important processes in the upper atmosphere relating to solar and energetic particle input, atmospheric response, and ion outflow. PISA measures in-situ irregularities in electron number density, TTI provides limb measurements of the atomic oxygen temperature profile with altitude, and MINI-ME provides a unique look at ion populations by a remote sensing technique involving neutral atom imaging. Together with other instruments and payloads on STP-S26 such as the NSF RAX mission, FalconSat-5, and NanoSail-D (launched as a tertiary payload from FASTSAT), these instruments provide a valuable “constellation of opportunity” for following the flow of energy and charged and neutral particles through the upper atmosphere. Together, and for a small fraction of the price of a major mission, these spacecraft will measure the energetic electrons impacting the upper atmosphere, the ions leaving it, and the large-scale plasma and neutral response to these energy inputs. The result will be a new model for maximizing scientific return from multiple small, distributed payloads as secondary payloads on a larger launch vehicle.

Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LET/sub th/. The difference between LET/sub th/ at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.

Total dose and RT annealing effects on startup current transient in antifuse FPGA

The startup current in an antifuse field programmable gate array (FPGA) device, A1280A, is investigated in the context of ionizing radiation effects. If properly measured, a radiation induced startup transient (RIST) can be identified after certain amount of irradiation. RIST increases with total dose (TID), and is strongly dependent on the dose rate. Room-temperature biased annealing for few days can reduce RIST to a very low level. A transistor-level mechanism is proposed to elucidate the origin of RIST. The ionization induced leakage in the NMOS diode is believed to be the root cause. The degradation of the ramping speed of the charge pump causes RIST when powering up the device. SPICE simulation was also performed to demonstrate the slow down of the ramping speed by the leakage in the NMOS diode. In typical low-dose-rate space environments, RIST is not the limiting factor for the total dose tolerance.

Back to the moon: The verification of a small microprocessor’s logic design

The original and primary task of self-test program Smalley3 was independent verification of the logic design of the LOLA DU (lunar orbiter laser altimeter digital unit) microprocessor. Tasks were added to verify continuing correct operation of this central processing unit (CPU) under margin testing for supply voltage, ambient temperature, and clock frequency. Finally, an on-orbit diagnostic task was added so that any malfunctions of LOLA in lunar orbit can be identified as faults in, or not in, the CPU. The Lunar Reconnaissance Orbiter spacecraft will be launched to the Moon in 2009 with six scientific instruments including LOLA, each containing an embedded microprocessor to perform real-time subsystem control calculations. LOLAs CPU is a small, custom-designed processor, designed to meet the mission requirements while minimizing resources. This 8-bit machine is essentially code compatible with Intels 8085 but is implemented in modern technology, an advanced, radiation-hardened 0.15 mum gate array, with the only logic element types being a 4:1 multiplexor and a flip-flop. This paper explains the fundamental structure of the verification task, shows how particular instructions are verified, presents a high-coverage scheme for detecting inadvertent RAM alteration, describes subsystem testing of RAM, and reviews the results of the verification effort. Some infamous CPU design flaws from both the commercial industry and aerospace flight control systems are discussed.