John McCollum

Dielectric based antifuse for logic and memory ICs

The authors describe a programmable low-impedance circuit element (PLICE), which is a dielectric-based antifuse for use in both logic and memory ICs. The antifuse element offers significant size and performance improvement compared to other programmable cells. A simple thermal model has been developed to predict the antifuse resistance. Each antifuse occupies an area of 1.5- mu m/sup 2/ using 1.2- mu m technology. It can be programmed within 1 ms and has a tight resistance distribution centered around 500 Omega . The reliability of both the programmed and unprogrammed states is demonstrated to be better than 40 years. The antifuse was used in the design of the first family of desktop-configurable channeled gate arrays and a 64 K PROM (programmable read-only memory) device.<<ETX>>

A CMOS electrically configurable gate array

A CMOS electrically configurable gate array that combines the flexibility, efficiency, extendability, and performance of mask-programmed gate arrays with the convenience of user programmability is described. The implementation is facilitated by a novel two-terminal antifuse programmable element and a configurable interconnect technology. The chip has been fabricated using 2- mu m n-well CMOS technology with two-layer metallization. >

New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs

New single event transient characterization and mitigation techniques unique for nonvolatile field programmable gate arrays (FPGAs) are investigated. Their implementation on a flash-based FPGA and evaluation in-beam show their efficacy with little area overhead but moderately high time penalty for highly scaled technologies.

Characterization and modeling of a highly reliable metal-to-metal antifuse for high-performance and high-density field-programmable gate arrays

The reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled. Unprogrammed antifuse leakage and time-to-breakdown are functions not only of applied voltage but also of stressing polarity and temperature. Both breakdown and leakage criteria are used to investigate their effects on time-to-fail. A thermal model incorporates the effects of programming and stress currents, ambient temperature, and variation of antifuse resistance with temperature. The measured temperature dependence of antifuse resistance is used for the first time to derive key physical parameters in the model.

Total ionizing dose effects on flash-based field programmable gate array

The total ionizing dose effect on a commercial Flash-based field programmable gate array is investigated by gamma ray radiation. The floating-gate threshold and logic propagation delay are measured with respect to the total dose. A physical model is also developed to express the threshold in terms of total dose for both unbiased- and biased-radiation conditions. Experimental data of the threshold fit this model for extracting the modeling parameters. The modeling predictions match further experimental data very well for low to moderate total dose. Using modeling and SPICE simulation together, the prediction of the propagation delay is compared to the experimental data. The biased condition has a good fit while the unbiased prediction over-degrades the propagation delay with respect to the experimental data.

Configuration and Routing Effects on the SET Propagation in Flash-Based FPGAs

New insights on SET propagation in flash-based FPGAs are investigated, with regards to their technology and unique non-volatile architecture. By means of SET fault injection tests, the broadening and the filtering of SET pulse widths were demonstrated and are related to the SET pulse transition and data-path in the studied FPGA design. These basic mechanisms result in a clear dependence of the SET pulse width on the designs configuration and routing that would favor spontaneous SET filtering in most real life designs.

New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P

Heavy-ion and proton test results utilizing novel test methodologies of reprogrammable and non-volatile flash-based FPGAs are presented and discussed. The 5 programmable architectures in the A3P FPGA-family were tested: I/O structures, FPGA Core, PLL, FROM and SRAM. Furthermore, the circuitry used for the programming and the erase of the A3P product was exercised in proton beams. The data shows no major concern or disruption to all of the circuit features for fluences lower than 1011 particles or TID higher than 15 Krad.

Oxide-nitride-oxide antifuse reliability

Compact, low-resistance oxide-nitride-oxide (ONO) antifuses are studied for time-dependent dielectric breakdown (TDDB), program disturb, programmed antifuse resistance stability, and effective screen. ONO antifuses are superior to oxide antifuses. No ONO antifuse failures were observed in 1.8 million accelerated burn-in device-hours accumulated on 1108 product units. This is in agreement with the 1/E field acceleration model.<<ETX>>

Single event upset and hardening in 0.15 /spl mu/m antifuse-based field programmable gate array

The single event effects and hardening of a 0.15 /spl mu/m antifuse FPGA, the AX device, were investigated by beam test and computer simulation. The beam test showed no permanent damage mode. Functional failures were observed and attributed to the upsets in a control logic circuit, the startup sequencer. Clock upsets were observed and attributed to the single event transients in the clock network. Upsets were also measured in the user flip-flop and embedded SRAM. The hardening technique dealing with each upset mode is discussed in detail. SPICE and three-dimensional mixed-mode simulations were used to determine the design rules for mitigating the multiple upsets due to glancing angle and charge sharing. The hardening techniques have been implemented in the newly fabricated RTAXS device. Preliminary heavy-ion-beam test data show that all the hard-wired hardening solutions are working successfully.

Investigation of Low Dose Rate and Bias Conditions on the Total Dose Tolerance of a CMOS Flash-Based FPGA

TID test results of CMOS Flash-based FPGAs in gamma-rays are presented. The use of realistic low dose-rates and oriented bias-conditions are shown to extend the FPGA TID tolerance. Implications to qualification methods and to most of the new CMOS technologies are noted.