B. Cronquist

Radiation effects on current field programmable technologies

Manufacturers of field programmable gate arrays (FPGAs) take different technological and architectural approaches that directly affect radiation performance. Similar technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed.

New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs

New single event transient characterization and mitigation techniques unique for nonvolatile field programmable gate arrays (FPGAs) are investigated. Their implementation on a flash-based FPGA and evaluation in-beam show their efficacy with little area overhead but moderately high time penalty for highly scaled technologies.

Current radiation issues for programmable elements and devices

State of the art programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper discusses that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers modifications to their COTS-based devices and their impact on future programmable devices are analyzed.

Total ionizing dose effects on flash-based field programmable gate array

The total ionizing dose effect on a commercial Flash-based field programmable gate array is investigated by gamma ray radiation. The floating-gate threshold and logic propagation delay are measured with respect to the total dose. A physical model is also developed to express the threshold in terms of total dose for both unbiased- and biased-radiation conditions. Experimental data of the threshold fit this model for extracting the modeling parameters. The modeling predictions match further experimental data very well for low to moderate total dose. Using modeling and SPICE simulation together, the prediction of the propagation delay is compared to the experimental data. The biased condition has a good fit while the unbiased prediction over-degrades the propagation delay with respect to the experimental data.

Configuration and Routing Effects on the SET Propagation in Flash-Based FPGAs

New insights on SET propagation in flash-based FPGAs are investigated, with regards to their technology and unique non-volatile architecture. By means of SET fault injection tests, the broadening and the filtering of SET pulse widths were demonstrated and are related to the SET pulse transition and data-path in the studied FPGA design. These basic mechanisms result in a clear dependence of the SET pulse width on the designs configuration and routing that would favor spontaneous SET filtering in most real life designs.

Radiation Hardened FPGA Technology for Space Applications

High performance, high density, radiation hardened Field Programmable Gate Arrays (FPGAs) are in great demand for military and space applications to reduce design cost and cycle time. BAE Systems has implemented radiation hardened 150nm bulk CMOS process technology in its foundry located in Manassas, VA to support such advanced product needs. BAE Systems and Actel Corporation are collaborating to bring the next-generation radiation hardened FPGA product for space applications to market. This paper will describe the rad hard AX-250 FPGA and the electrical and radiation test data on rad hard 150nm product hardware, FPGA device structures and anti-fuse arrays, as part of the overall FPGA product installation and qualification effort.

New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P

Heavy-ion and proton test results utilizing novel test methodologies of reprogrammable and non-volatile flash-based FPGAs are presented and discussed. The 5 programmable architectures in the A3P FPGA-family were tested: I/O structures, FPGA Core, PLL, FROM and SRAM. Furthermore, the circuitry used for the programming and the erase of the A3P product was exercised in proton beams. The data shows no major concern or disruption to all of the circuit features for fluences lower than 1011 particles or TID higher than 15 Krad.

A Novel Flash-based FPGA Technology with Deep Trench Isolation

A highly scalable flash-based Field Programmable Gate Array (FPGA) technology has been achieved with Deep Trench Isolation (DTI). The DTI allows for a reduced cell size and enables Independent Pwell (IPW) array operation. The IPW FPGA array operation requires less than + 10 V during Uniform Channel FN-FN programming and shows negligible gate disturb. Additionally, it eliminates Gate-Induced Drain Leakage (GIDL) during programming. Characterization of a FPGA cell and array with 90 nm design rules is demonstrated with excellent electrical characteristics.

Single event upset and hardening in 0.15 /spl mu/m antifuse-based field programmable gate array

The single event effects and hardening of a 0.15 /spl mu/m antifuse FPGA, the AX device, were investigated by beam test and computer simulation. The beam test showed no permanent damage mode. Functional failures were observed and attributed to the upsets in a control logic circuit, the startup sequencer. Clock upsets were observed and attributed to the single event transients in the clock network. Upsets were also measured in the user flip-flop and embedded SRAM. The hardening technique dealing with each upset mode is discussed in detail. SPICE and three-dimensional mixed-mode simulations were used to determine the design rules for mitigating the multiple upsets due to glancing angle and charge sharing. The hardening techniques have been implemented in the newly fabricated RTAXS device. Preliminary heavy-ion-beam test data show that all the hard-wired hardening solutions are working successfully.

Comprehensive SEE characterization of 0.13µm flash-based FPGAs by heavy ion beam test

Heavy-ion test results utilizing novel test methodologies of reprogrammable and non-volatile flash-based FPGAs are presented and discussed. The 5 programmable architectures in the A3P FPGA-family were tested: I/O structures, FPGA Core, PLL, FROM and SRAM.