Jih-Jong Wang

SRAM based re-programmable FPGA for space applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 /spl mu/m CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor dc-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I/sub CC/) measured indicates a device tolerance of approximately 50 krad(Si).

New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs

New single event transient characterization and mitigation techniques unique for nonvolatile field programmable gate arrays (FPGAs) are investigated. Their implementation on a flash-based FPGA and evaluation in-beam show their efficacy with little area overhead but moderately high time penalty for highly scaled technologies.

Total ionizing dose effects on flash-based field programmable gate array

The total ionizing dose effect on a commercial Flash-based field programmable gate array is investigated by gamma ray radiation. The floating-gate threshold and logic propagation delay are measured with respect to the total dose. A physical model is also developed to express the threshold in terms of total dose for both unbiased- and biased-radiation conditions. Experimental data of the threshold fit this model for extracting the modeling parameters. The modeling predictions match further experimental data very well for low to moderate total dose. Using modeling and SPICE simulation together, the prediction of the propagation delay is compared to the experimental data. The biased condition has a good fit while the unbiased prediction over-degrades the propagation delay with respect to the experimental data.

Configuration and Routing Effects on the SET Propagation in Flash-Based FPGAs

New insights on SET propagation in flash-based FPGAs are investigated, with regards to their technology and unique non-volatile architecture. By means of SET fault injection tests, the broadening and the filtering of SET pulse widths were demonstrated and are related to the SET pulse transition and data-path in the studied FPGA design. These basic mechanisms result in a clear dependence of the SET pulse width on the designs configuration and routing that would favor spontaneous SET filtering in most real life designs.

Radiation Hardened FPGA Technology for Space Applications

High performance, high density, radiation hardened Field Programmable Gate Arrays (FPGAs) are in great demand for military and space applications to reduce design cost and cycle time. BAE Systems has implemented radiation hardened 150nm bulk CMOS process technology in its foundry located in Manassas, VA to support such advanced product needs. BAE Systems and Actel Corporation are collaborating to bring the next-generation radiation hardened FPGA product for space applications to market. This paper will describe the rad hard AX-250 FPGA and the electrical and radiation test data on rad hard 150nm product hardware, FPGA device structures and anti-fuse arrays, as part of the overall FPGA product installation and qualification effort.

New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P

Heavy-ion and proton test results utilizing novel test methodologies of reprogrammable and non-volatile flash-based FPGAs are presented and discussed. The 5 programmable architectures in the A3P FPGA-family were tested: I/O structures, FPGA Core, PLL, FROM and SRAM. Furthermore, the circuitry used for the programming and the erase of the A3P product was exercised in proton beams. The data shows no major concern or disruption to all of the circuit features for fluences lower than 1011 particles or TID higher than 15 Krad.

Biased-Irradiation Characteristics of the Floating Gate Switch in FPGA

The radiation characteristic of the floating-gate switch in a 0.22 mum flash-based FPGA is investigated by measuring the threshold voltage after each stage of X-ray irradiation. The focus is on the applied bias on the floating-gate device during irradiation. A two-parameter, semi-physical model is used to fit the experimental results. For an erase or write state with a particular irradiation-bias, a set of two fitting parameters can accurately determine the threshold voltage with respect to total radiation dose. The modeling result can be easily integrated into the SPICE simulator for circuit design purposes

Single event upset and hardening in 0.15 /spl mu/m antifuse-based field programmable gate array

The single event effects and hardening of a 0.15 /spl mu/m antifuse FPGA, the AX device, were investigated by beam test and computer simulation. The beam test showed no permanent damage mode. Functional failures were observed and attributed to the upsets in a control logic circuit, the startup sequencer. Clock upsets were observed and attributed to the single event transients in the clock network. Upsets were also measured in the user flip-flop and embedded SRAM. The hardening technique dealing with each upset mode is discussed in detail. SPICE and three-dimensional mixed-mode simulations were used to determine the design rules for mitigating the multiple upsets due to glancing angle and charge sharing. The hardening techniques have been implemented in the newly fabricated RTAXS device. Preliminary heavy-ion-beam test data show that all the hard-wired hardening solutions are working successfully.

Comprehensive SEE characterization of 0.13µm flash-based FPGAs by heavy ion beam test

Heavy-ion test results utilizing novel test methodologies of reprogrammable and non-volatile flash-based FPGAs are presented and discussed. The 5 programmable architectures in the A3P FPGA-family were tested: I/O structures, FPGA Core, PLL, FROM and SRAM.

SET and SEFI Characterization of the 65 nm SmartFusion2 Flash-Based FPGA under Heavy Ion Irradiation

SET and SEFI characterization of the SmartFusion2 flash-based FPGA under heavy ion irradiation is presented. Functional blocks such as the PLL and Microcontroller Sub System are characterized and presented.