Ikuo Nishioka

An Automatic Routing Scheme for General Cell LSI

An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown.

SHARPS: A Hierarchical Layout System for VLSI

A hierarchical layout system for VLSI provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. Several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom LSIs.

A Placement Algorithm for Polycell LSI and its Evaluation

An automatic placement algorithm for standard cell and polycell LSI is described, which is constructed on the basis of heuristics for a set of interrelated placement subproblems. The algorithm is incorporated into a hierarchical layout system intended not only for standard cell and polycell LSI but for general cell LSI, by which standard cell and polycell LSI have begun to be laid out in practice. A part of implementation results are also shown to reveal how high the layout performance of the placement program.

An Approach to Gate Assignment and Module Placement for Printed Wiring Boards

High density packaging is one of the most urgent requirements in the design of digital systems. In the assembly of such systems, printed wiring boards (PWBs) are used very often to provide the necessary interconnection among circuit modules. Thus, methods to raise wiring density of PWBs are continually under investigation. Given a router to realize 100 percent wiring, an efficient method for assigning logical gates to circuit modules and for determining the placement of the modules on a given PWB may contribute more toward raising the wirability than improving the existing routing scheme, especially when all available sophisticated routing algorithms have been attempted. The present paper proposes an algorithm to the problem of gate assignment and module placement, to be added to an existing router. It operates on a PDP 11/40 with 24K words core memory and 1.2M words disk storage coupled with a TEKTRONIX 4014 graphics terminal. We also show how effectively the described assignment and placement scheme improves the wirability of the router.

Automated generation of simply connected solid objects from wire-frame data using operations on graphs

This paper presents an algorithm for the automatic generation of solid objects from three-dimensional wire-frame data. In this work, as we mainly use topological information of wire-frame data, we can achieve high-speed execution and adapt this algorithm to free-from surfaces. We present the conversion algorithm and show several experimental results.

Development of a Total 3D CAD/CAM System for Electric Appliances

This paper presents an overview of a 3D CAD/CAM system for electric appliances. The distinctive features of the system are as follows; 1 The system supports a wide range of design activities, conceptual design, engineering design and production design. 2 The system enables a conceptual designer to evaluate design options based on realistic representations of objects. 3 Various kinematic simulation functions enable engineers to analyze mechanisms.

An Automatic Routing System for High Density Multilayer Printed Wiring Boards

Recent advances in the packaging technology of microelectronics have changed the design rules for printed wiring boards (PWBs) such that the number of wiring tracks between adjacent pins of an ordinary dual in line package (DIP) is allowed to be two or more, and the number of signal layers to be laminated is often required to be four or more. When the packaging density or scale of a PWB augments to such an extent, conventional routing schemes are confronted with various difficulties. The present paper describes a new routing system which can cope with such high density PWBs, for which the maximum numbers of layers to be laminated, circuit modules to be mounted, and signal nets are admitted up to 16, 2,000 and 4,000, respectively. The system described operates on a PDP 11/34 computer coupled with a TEKTRONIX 4014 graphics terminal. A set of implementation results are also shown to reveal how much the described system contributes to the reduction of time and labor incurred in laying out multilayer PWBs of high density.

An Interactive Layout System for Analog Printed Wiring Boards

Apart from the layout of digital printed wiring boards (PWBs), no specific development has yet been reported on the layout of analog PWBs, which requires not only placement and routing but also artwork to generate a variety of geometric wire patterns and assembly drawings. An interactive artwork system for analog PWBs is described, which consists mainly of two programs; one for generating wire patterns and the other for generating assembly drawings. This system is in production use and has greatly reduced the time and cost incurred in laying out wire patterns on analog PWBs.

An Interactive Layout System of Analog Printed Wiring Boards

Apart from the layout of digital printed wiring boards (PWBs), no specific development has yet been reported on the layout of analog PWBs which contains not only placement and routing but also artwork to generate a variety of geometric wire patterns and assembly drawings, according to specifications. In this paper, we describe an interactive artwork system for such analog PWBs, which consists mainly of two programs; one is for generating wire patterns, and the other is for generating assembly drawings. This system has been in production use and has greatly contributed to the reduction of time and cost incurred in laying out wire patterns on analog PWBs.