Takashi Kambe

Hybrid floorplanning based on partial clustering and module restructuring

In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during iterative improvement are proposed: (1) Partial Clustering, and (2) Module Restructuring. These strategies work for localizing nets connecting small modules in small regions, and conceal such small modules and their nets during the iterative improvement phase. This method is successful in reducing both area and wire length in addition to reducing the computational time required for optimization. Although our method only searches slicing floorplans, the results are superior to the results obtained even with non-slicing floorplans. We applied our method to the largest MCNC floorplan benchmark example, ami49, and industrial data. For the ami49 benchmark, we obtained results superior to any published results for both estimated area and routing results.

Hardware synthesis with the Bach system

We describe the Bach hardware synthesis system from parallel algorithms, allowing users to design, verify and synthesize large and complex circuits. Each is a working tool which is already being used for full-scale commercial designs. The source language is based on ANSI C with extensions to support explicit parallelism, communications and bit-width specification. We demonstrate its effectiveness by evaluating industrial strength applications.

A testability analysis method for register-transfer level descriptions

In this paper, we propose a new testability analysis method for Register-Transfer Level (RTL) descriptions. The proposed method is based on the idea of testability analysis in terms of data-flow and control structure which can be extracted from RTL designs. We analyze testability of RTL descriptions with more testability measures than those of conventional gate-level testability, so that the method provides information for design for testability (DFT). We have implemented the presented method and experimental results show that we can reduce circuit cost for test and achieve highly testable circuits by DFT using our RTL testability analysis.

A scheduling method for synchronous communication in the Bach hardware compiler

In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the prescheduling result. Consequently, we can synthesize large system LSIs efficiently, because we do not need to synthesize the whole system descriptions at once to synchronize communications. Experimental results show that our method improves throughput of synthesized circuits and is applicable to large systems designed with the Bach hardware compiler.

A layout approach to monolithic microwave IC

A layout approach is described dedicatedly for MMICs, in which layout elements are transistors, inductors, capacitors, resistors, coplanar-waveguides, etc., implemented by GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orientating constraints as well as shaping variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is effectively applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

C-based design of a real time speech recognition system

Speech recognition is becoming a popular technology for the implementation of human interfaces. However, conventional approaches to large vocabulary continuous speech recognition require a high performance CPU. In this paper, we describe a speech-recognition system designed using a C-based design methodology and compare three hardware implementations for the computationally intensive parts. Pipelining, parallel processing and cache memory solutions to compute the hidden Markov model (HMM) output probability at high speed were implemented and their performances evaluated. It is shown that designers can rapidly explore a wide range of complex circuits in a using this methodology and that real time speech recognition in small portable systems is possible

C-based system LSI design of a particle tracking technology

The size and performance of a system LSI depend heavily on the architecture which is chosen. As a result, the architecture design phase is one of the most important steps in the system LSI development process and is critical to the commercial success of a device. In this paper, we propose a C-based system LSI design methodology and apply it to the design of of a software and hardware system based on the particle mask correlation (PMC) method and the KC method. The computational overhead is accelerated by the use of secondary differentiation preprocessing, 1-mask processing, cache memory utilization, area limitation of the particle search, and function-level pipelining. The processing speed, the circuit size of the system are evaluated.

A layout approach to Monolithic Microwave IC

A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout elements under a variety of spacing, orientating, and shaping constraints. Each layout element is modeled to simplify placement tasks subject to different placement constraints, and then a set of the interconnection requirements among elements is represented by a graph, to which a planarization algorithm is effectively applied. As a result of this planarization, a placement procedure is constructed mainly by repeated application of a merging scheme. A number of experimental results are also shown to demonstrate the practicability of the described layout approach.

Application-specific arithmetic circuit design for a particle tracking application

The main bottleneck in system LSI performance is, in many cases, the processing overhead that occurs when arithmetic calculations are performed multiple times. The circuit size and processing time required for multiplication, division and other basic arithmetic operations are often especially large. In this paper we propose an application-specific arithmetic circuit design methodology and apply it to the design of a correlation coefficient calculation circuit for a particle tracking application. Particle tracking velocimetry (PTV) measures velocity fluctuations in fluids and gases and has been applied to a diverse range of flows. However, the algorithms are computationally intensive so to achieve real-time processing speeds implementation in hardware is essential. The computational overhead is accelerated by applying code refactoring, memory access optimization, and variable length pipelining. The processing speed and the circuit size of the design are evaluated. We show that the hardware solution is 1,000 times faster than the software solution and is able to achieve real-time processing speeds.

A new delay distribution model to take long-term degradation into account

The long-term degradation due to aging such as NBTI (Negative Bias Temperature Instability) is a hot issue in the current circuit design using nanometer process technologies, since it causes a delay fault in the field. In order to resolve the problem, we must estimate delay variation caused by long-term degradation in design stage, but over estimation must be avoided so as to make timing design easier. If we can treat such a variation statistically, and if we treat it together with delay variations due to process variability, then we can reduce over margin in timing design. Moreover, such a statistical static timing analyzer treating process variability and long-term degradation together help us to select an appropriate set of paths for which field testing are conducted to detect delay faults. In this paper, we propose a new delay model taking long-term degradation into account for statistical static timing analysis, and propose an algorithm for finding the statistical maximum, which is one of key operations in statistical static timing analysis. We also show a few experimental results demonstrating the effect of the algorithm.