In-Chul Jeong

1.2V 1.6Gb/s 56nm 6F 2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

As the workload and speed of a computer system increase, both the data bandwidth and capacity of main memory inevitably need to grow. However, the number of slots per channel is limited to maintain high bandwidth, making the capacity requirement difficult to meet. Another problem is that computer systems impose a limit on the supply of power since their power dissipation increases rapidly, where main memories account for roughly 15% of total power consumption. To address these issues, we design a 4Gb DDR3 SDRAM that supports a 1.2V supply voltage and 1.6Gb/s data rate.